• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1824-1826
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• 2000

Up to date, the dual scanning method has been adopted to decrease address-ing period in AC PDP. In this case, addressing period can be reduced, but the driving circuit cost should be increased. In this study, to increase addressing speed we have studied the relationship between addressing speed and cell structure. That is to say, we varied the thickness of dielectric layer on the front glass, the thickness of white back and the height of barrier rib on the rear glass. So, we found that the addressing time was decreased 4% with decreasing 5um thickness of dielectric layer on the front glass and 2um thickness of white back on the rear glass. Also in case of decreasing the height of barrier rib, addressing time was decreased about 4% per 10um.

• Structural Engineering and Mechanics
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• 제83권1호
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• pp.53-66
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• 2022

The main objective of the present research was investigating the effects of a floating wave barrier installed in front of an offshore jacket structure on the wave height, base shear, and overturning moment. A jacket model with the height of 4.55 m was fabricated and tested in the 402 m-long wave flume of NIMALA marine laboratory. The jacket was tested at the water depth of 4 m subjected to the random waves with a JONSWAP energy spectrum. Three input wave heights were chosen for the tests: 20 cm, 23 cm, and 28 cm. Two different cross sections with the same area were selected for the wave barrier: square and rhombus. Results showed that the average decrease in the jacket's base shear due to the presence of a floating wave barrier with square and rhombus cross section was 24.67% and 34.29%, respectively. The use of wave barriers with square and rhombus cross sections also resulted in 19.78% and 33.11% decrease in the jacket's overturning moment, respectively. Hence, it can be concluded that a floating wave barrier can significantly reduce the base shear and overturning moment in an offshore jacket structure; and a rhombus cross section is more effective than an equivalent square section.

• 한국자기학회지
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• 제13권2호
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• pp.47-52
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• 2003

DC 마그네트론 스파터법과 RLSA(Radial Line Slot Antenna)을 이용한 마이크로파 여기 프라즈마를 이용하여 Ta/Cu/Ta/NiFe/Cu/Mn$_{75}$Ir$_{25}$/ $Co_{70}$Fe$_{30}$/Al-oxide 구조의 접합을 제조한 후, contact-mode AM(Atomic Force Microscope)을 이용하여 Al 산화막의 국소전도 특성의 평가를 수행하였다. AFM 동시전류측정으로부터, 얻어지는 표면상과 전류상은 대응하지 않는다. 국소 전류-전압(I-V)의 측정 결과, 전류상은 절연층의 barrier height의 분포를 나타내고 있다는 것을 알았다.다.다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2000년도 제18회 학술발표회 논문개요집
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• pp.113-113
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• 2000

직접천이형 wide band gap(3.4eV) 반도체중의 하나인 GaN를 청색 및 자외선 laser diode, 고출력 전자장비 등으로 응용하기 위해서는 낮은 접합저항을 갖는 Ohmic contact이 선행되어야 한다. 그러나 만족할만한 p-type GaN의 Ohmic contact은 아직 실현되고 있지 못하며, 이는 GaN와 접합 금속과의 구체적인 반응의 연구를 필요로 한다. 본 연구에서 앞서 Pt, Pt, Ni등의 late transition metal을 p-GaN에 접합시킨 결과 이들은 접합 당시 비교적 평탄하나 후열 처리과정에서 비교적 낮은 온도에서 기판과 열팽창계수의 차이로 인하여 평탄성을 잃어버리면서 barrier height가 증가한다는 사실을 확인하였다. 따라서 본 연구에서는 이러한 열적 불안정성을 극복하기 위하여 Ni과 Pd를 차례로 증착하고 가열하면서 interfacial reaction, film morphology, Fermi level의 움직임을 monchromatic XPS(x-ray photoelectron spectroscopy) 와 SAM(scanning Auger microscopy) 그리고 ex-situ AFM을 이용하여 밝히고자 하였다. 특히 후열처리에 의한 계면 반응에 수반되는 구성 금속원소 간의 합금현상과 금속 층의 평탄성이 밀접한 관계가 있다는 것을 확인하였다. 이러한 합금과정에서 나타나는 금속원소들의 중심 준위의 이동을 체계적으로 규명하기 위해서 Pd1-xNix와 Pd1-xGax 합금들의 표준시료를 arc melting method로 만들어 농도에 따른 금속원소들의 중심 준위의 이동을 측정하여, Pd/Ni/p-GaN 및 Ni/Pd/p-GaN 계에서 열처리 온도에 따른 interfacial reaction을 확인하였다. 그 결과 두 계가 상온에서 nitride 및 alloy를 형성하지 않고 고르게 증착되고, 열처리 온도를 40$0^{\circ}C$에서 $650^{\circ}C$까지 증가시킴에 따라 계면반응의 부산물인 metallic Ga은 증가하고 있으마 nitride는 여전히 형성되지 않는 것을 확인하였다. 증착당시 Ni이 계면에 있는 Pd/Ni/p-GaN의 경우에는 52$0^{\circ}C$까지의 열처리에 의하여 Ni과 Pd가 골고루 섞이고 그 평탄성도 유지되고 barier height의 변화도 없었다. 더 높은 $650^{\circ}C$ 가열에 의해서는 surface free energy가 작은 Ga의 활발한 편석 현상으로 인해 표면은 Ga이 풍부한 Pd-Ga의 합금층으로 덮이고, 동시에 작은 pinhole들이 발생하며 barrier height도 0.3eV 가량 증가하게 된다. 반면에 증착당시 Pd이 계면에 있는 Ni/Pd/p-GaN의 경우에는 40$0^{\circ}C$의 가열까지는 두 금속이 그들 계면에서부터 섞이나, 52$0^{\circ}C$의 가열에 의해 이미 barrier height가 0.2eV 가량 증가하기 시작하였다. 더 높은 $650^{\circ}C$가열에 의해서는 커다란 pinhole, 0.5eV 가량의 barrier height 증가, Pd clustering이 동시에 관찰되었다. 따라서 Ni과 Pd의 일함수는 물론 thermal expansion coefficient가 거의 같으며 surface free energy도 거의 일치한다는 점을 감안하면, 이렇게 뚜렷한 열적 안정성의 차이는 GaN와 contact metal과의 반응시작 온도(disruption onset temperature)의 차이에 기인함을 알 수 있었다. 즉 계면에서의 반응에 의해 편석되는 Ga에 의해 박막의 strain이 이완되면, pinhole 등의 박막결함이 줄어 들고, 이는 계면의 N의 out-diffusion을 방지하여 p-type GaN의 barrier height 증가를 막게 된다.

• Transactions on Electrical and Electronic Materials
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• 제17권5호
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• pp.293-296
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• 2016

Using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements, the electrical properties of Cu/n-InP Schottky diodes were investigated. The values of C and G/ω were found to decrease with increasing frequency. The presence of interface states might cause excess capacitance, leading to frequency dispersion. The negative capacitance was observed under a forward bias voltage, which may be due to contact injection, interface states or minority-carrier injection. The barrier heights from C-V measurements were found to depend on the frequency. In particular, the barrier height at 200 kHz was found to be 0.65 eV, which was similar to the flat band barrier height of 0.66 eV.

• 한국전기전자재료학회논문지
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• 제14권7호
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• pp.533-538
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• 2001

The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

• 한국전기전자재료학회논문지
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• 제15권12호
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• pp.1065-1069
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• 2002

The addressing time should be reduced by modifying cell structure and/or driving method in order to replace the dual scan system by single scan and increase the luminance in large ac plasma display panel(PDP). In this paper, the effects of the addressing time was decreased with decreasing thickness of dielectric layer on the front glass and thickness of white dielectric layer on the rear glass. the decreasing rate were 160ns/10$\mu\textrm{m}$ and 270ns/10$\mu\textrm{m}$, respectively Also in case of decreasing the height of barrier rib, addressing time was decreased at the rate of Sons/10$\mu\textrm{m}$.

• The Korean Journal of Ceramics
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• 제4권1호
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• pp.37-42
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• 1998

The barrier heights and carrier densities of ZnO varistors with various compositions were estimated using C-V, J-V and $\rho$-T relations. The barrier heights obtained from C-V and J-V plots were 0.73~5.98 eV and 0.25~2.70 eV, respectively. The carrier densities estimated from C-V plots were ~$10^{18}cm^{-3}$. Acceptable values of the barrier heights and the carrier densities were obtained from $\rho$-1/T curves and the capacitances at zero bias; 0.6~0.8 eV for the barrier heights and ~$10^{17}cm^{-3}$ for carrier densities. Addition of cobalt increased the barrier height and the carrier density, while chromium slightly lowered both of them.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.177-179
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• 2000

Barrier rib for the plasma display panel (PDP) was made by photolithographic process utilizing photosensitive barrier rib paste. The barrier rib paste was prepared by first dissolving poly(MMA-co-MAA) binder polymer in butyl carbitol(BC) solvent at 15 wt% concentration. To this solution were added a mixture of functional monomers , Irgacure 651 photoinitiator, and barrier rib power and then the whole mixture was dispersed in the three roll mill for 2 hour. The effect of component and concentration of photosensitive barrier rib paste was studied. After optimization of the paste formulation and photolithographic process, barrier rib could be obtained with good resolution up to 110-120 ${\mu}m$ height and 80-90 ${\mu}m$ width.