• Title/Summary/Keyword: Balancer design

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Small signal Analysis and Controller Design of Interleaved Voltage Balancer with Coupled Inductor (커플드 인덕터 인터리브드 전압 밸런서의 소신호 분석 및 제어기 설계)

  • Byun, Hyung-Jun;Park, Jung-Min;Park, Tae-Hwa;Kim, Bum-Jun;Won, Chung-Yuen
    • Proceedings of the KIPE Conference
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    • 2019.11a
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    • pp.112-113
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    • 2019
  • 본 논문은 양극성 저압 직류배전망 구성을 위한 커플드 인덕터를 활용한 인터리브드 전압 밸런서의 소신호 분석 및 제어기 설계를 제안한다. 커플드 인덕터를 활용한 인터리브드 구조의 전압 밸런서는 출력 캐패시턴스 및 전체 인덕턴스를 줄일 수 있는 이점 있으나, 결합계수 및 인터리브드 입력으로 인한 회로 분석의 어려움이 존재한다. 본 논문은 이를 해결하기 위해 커플드 인덕터 등가회로를 통한 인덕턴스 결합 분석 및 제어 입력의 평균 계산법을 적용하여 소신호 모델링을 진행하고 제어기를 설계하였으며 이를 PSIM 시뮬레이션을 통해 검증하였다.

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Design of Coupled Inductor for Voltage Balancer in Biploar LVDC (양극성 저압 직류배전망 연계용 전압밸런서를 위한 커플드 인덕터 설계)

  • Byun, Hyung-Jun;Park, Jung-Min;Park, Tae-Hwa;Won, Chung-Yuen
    • Proceedings of the KIPE Conference
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    • 2019.07a
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    • pp.322-323
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    • 2019
  • 본 논문은 커플드 인덕터를 활용한 인터리브드 벅-부스트 전압밸런서를 제안한다. 기존 인터리브드 벅-부스트의 경우 부하 전류 리플을 줄이기 위해 다수의 자성소자를 사용하여 부피가 커지는 단점이 존재한다. 제안하는 방식은 기존 토폴로지에 비해 자성소자 수 및 인덕턴스를 줄일 수 있어 전체 토폴로지의 부피가 작아지는 이점을 갖는다. 본 논문에서는 인터리브드 벅-부스트 형 전압밸런서를 위한 커플드 인덕터 설계 사항 및 이점들을 제시한다.

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A High-Voltage Compliant Neural Stimulation IC for Implant Devices Using Standard CMOS Process (체내 이식 기기용 표준 CMOS 고전압 신경 자극 집적 회로)

  • Abdi, Alfian;Cha, Hyouk-Kyu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.5
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    • pp.58-65
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    • 2015
  • This paper presents the design of an implantable stimulation IC intended for neural prosthetic devices using $0.18-{\mu}m$ standard CMOS technology. The proposed single-channel biphasic current stimulator prototype is designed to deliver up to 1 mA of current to the tissue-equivalent $10-k{\Omega}$ load using 12.8-V supply voltage. To utilize only low-voltage standard CMOS transistors in the design, transistor stacking with dynamic gate biasing technique is used for reliable operation at high-voltage. In addition, active charge balancing circuit is used to maintain zero net charge at the stimulation site over the complete stimulation cycle. The area of the total stimulator IC consisting of DAC, current stimulation output driver, level-shifters, digital logic, and active charge balancer is $0.13mm^2$ and is suitable to be applied for multi-channel neural prosthetic devices.

Design and Implementation of Game Server using the Efficient Load Balancing Technology based on CPU Utilization (게임서버의 CPU 사용율 기반 효율적인 부하균등화 기술의 설계 및 구현)

  • Myung, Won-Shig;Han, Jun-Tak
    • Journal of Korea Game Society
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    • v.4 no.4
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    • pp.11-18
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    • 2004
  • The on-line games in the past were played by only two persons exchanging data based on one-to-one connections, whereas recent ones (e.g. MMORPG: Massively Multi-player Online Role-playings Game) enable tens of thousands of people to be connected simultaneously. Specifically, Korea has established an excellent network infrastructure that can't be found anywhere in the world. Almost every household has a high-speed Internet access. What made this possible was, in part, high density of population that has accelerated the formation of good Internet infrastructure. However, this rapid increase in the use of on-line games may lead to surging traffics exceeding the limited Internet communication capacity so that the connection to the games is unstable or the server fails. expanding the servers though this measure is very costly could solve this problem. To deal with this problem, the present study proposes the load distribution technology that connects in the form of local clustering the game servers divided by their contents used in each on-line game reduces the loads of specific servers using the load balancer, and enhances performance of sewer for their efficient operation. In this paper, a cluster system is proposed where each Game server in the system has different contents service and loads are distributed efficiently using the game server resource information such as CPU utilization. Game sewers having different contents are mutually connected and managed with a network file system to maintain information consistency required to support resource information updates, deletions, and additions. Simulation studies show that our method performs better than other traditional methods. In terms of response time, our method shows shorter latency than RR (Round Robin) and LC (Least Connection) by about 12%, 10% respectively.

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