• Journal of the Semiconductor & Display Technology
• /
• v.11 no.2
• /
• pp.71-74
• /
• 2012

Uniformity of the wafer temperature is one of the important factors in etching process. Plasma, chucking force, backside helium pressure and the surface temperature of ESC(electrostatic chuck) affect the wafer temperature. ESC consists of several layers of structure. Each layer has own thermal resistance and the Si-adhesive layer has highest thermal resistance among them. In this work, the temperature distribution of ESC was analyzed by 3-D FEM with various defects and the thickness deviation of the Si-adhesive layer. The result with Si-adhesive layer with the low center thickness deviation shows modified temperature distribution of ESC surface.

• Journal of Sensor Science and Technology
• /
• v.28 no.3
• /
• pp.152-156
• /
• 2019

An ultraviolet (UV) image sensor is an extremely important optoelectronic device used in scientific and medical applications because it can detect images that cannot be obtained using visible or infrared image sensors. Because photodetectors and transistors are based on different materials, conventional UV imaging devices, which have a hybrid-type structure, require additional complex processes such as a backside etching of a GaN epi-wafer and a wafer-to-wafer bonding for the fabrication of the image sensors. In this study, we developed a monolithic GaN UV passive pixel sensor (PPS) by integrating a GaN-based Schottky-barrier type transistor and a GaN UV photodetector on a wafer. Both individual devices show good electrical and photoresponse characteristics, and the fabricated UV PPS was successfully operated under UV irradiation conditions with a high on/off extinction ratio of as high as $10^3$. This integration technique of a single pixel sensor will be a breakthrough for the development of GaN-based optoelectronic integrated circuits.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2000.02a
• /
• pp.31-31
• /
• 2000

Al2O3는 높은 화학적, 열적 안정성으로 인하여 미세전자 산업에서 절연막이나 광전자소자의 재료로써 널리 이용되고 있다. 특히, 사파이어는 고위도의 LED, 청색 LD의 재료인 GaN 계열의 III-Nitride 물질을 성장시킬 때 필요한 기판으로 보편적으로 사용되고 있다. 이러한 GaN계열의 광소자 제조에서 사파이어 기판을 적용시 지적되는 문제점들 중의 하나는 소자제조 후 사파이어의 결정 구조 및 높은 경도에 의해 나타나는 cutting 및 backside의 기계적 연마가 어렵다는 것이다. 최근에는 이온빔 식각이나 이온 주입 후 화학적 습식 시각, reactive ion etching을 통한 사파이어의 건식 식각이 소자 분리 및 backside 공정을 우해 연구되고 있다. 그러나 이러한 방법을 이용한 사파이어의 식각속도는 일반적으로 15nm/min 보다 작다. 높은 식각율과 식각후 표면의 작은 거칠기를 수반한 사파이어의 플라즈마 식각은 소자 제조 공정시 소자의 isolation 및 lapping 후 연마 공정에 이용할 수 있다. 본 연구에서는 평판 유도결합형 플라즈마를 이용하여 Cl2/BCL3/Ar 의 가스조합, inductive power, bias voltage, 압력, 기판온도의 다양한 공정 변수를 통하여 (0001) 사파이어의 식각특성을 연구하였다. 사파이어의 식각속도는 inductive power, bias voltage, 그리고 기판 온도가 증가할수록 증가하였으며 Cl2에 BCl3를 50%이하로 첨가할 때 BCl3 첨가량이 증가할수록 식각속도 및 식각마스크(photoresist)와의 식각선택비가 증가하는 것을 관찰하였다. 또한, Cl3:BCl3=1:1의 조건에 따라 Ar 첨가에 따른 식각속도 및 표면 거칠기를 관찰하였다. 본 연구의 최적 식각조건인 40%Cl2/40%BCl3/20%Ar, 600W의 inductive power, -300V의 bias voltage, 30mTorr의 압력, 기판온도 7$0^{\circ}C$에서 270nm/min의 사파이어 식각속도를 얻을수 있었다. 그리고 이러한 식각조건에서 표면의 거치기를 줄일수 있었다. 사파이어 식각은 보편적인 사파이어 lapping 공정시 수반되어 형성된 표면의 거치기를 줄이기 위한 마지막 공정에 응용될수 있다. 사파이어의 식각시 나타나는 식각 부산물은 플라즈마 진단방비인 optical emission spectroscopy (OES)를 통하여 관찰하였고, 식각시 사파이어의 표면성분비 변화 및 표면의 화학적 결합은 X-ray photoelectron spectroscopy(XPS)를 사용하여 측정하였다. 시각 전, 후의 표면의 거칠기를 scanning electron microscopy(SEM)을 통하여 관찰하였다.

• Journal of Sensor Science and Technology
• /
• v.23 no.2
• /
• pp.114-121
• /
• 2014

We report a polysilicon active area membrane field effect transistor (PSAFET) pressure sensor for low stress deflection of membrane. The PSAFET was produced in conventional FET semiconductor fabrication and backside wet etching. The PSAFET located at the front side measured pressure change using 300 nm thin-nitride membrane when a membrane was slightly strained by the small deflection of membrane shape from backside with any physical force. The PSAFET showed high sensitivity around threshold voltage, because threshold voltage variation was composed of fractional function form in sensitivity equation of current variation. When gate voltage was biased close to threshold voltage, a fractional function form had infinite value at $V_{tn}$, which increased the current variation of sensitivity. Threshold voltage effect was dominant right after the PSAFET was turned on. Narrow transistor channel established by small current flow was choked because electron could barely cross drain-source electrodes. When gate voltage was far from threshold voltage, threshold voltage effect converged to zero in fractional form of threshold voltage variations and drain current change was mostly determined by mobility changes. As the PSAFET fabrication was compatible with a polysilicon FET in CMOS fabrication, it could be adapted in low pressure sensor and bio molecular sensor.

• Journal of Sensor Science and Technology
• /
• v.6 no.1
• /
• pp.72-80
• /
• 1997

One of the concerns in micro fluidic valve designs is that of reverse direction leakage. This paper designs and fabricates a new fluidic valve to achieve zero leakage. The design uses flapper and nozzle elements. In the forward direction the working fluid pushes the flapper upward to allow flow. In the reverse direction, the flapper pushes against the orifice seat, and thus, no flow can be generated, unless the flapper or nozzle element breaks. The nozzle element fabrication involves fabricating an orifice by wet etching of (100) wafer, The flapper element fabrication involves $20{\mu}m$ deep patterning of the negative image of the flapper, followed by wet etching from backside. Flow experiments were conducted with DI water as the working fluid, and the results are compared to analytical predictions. The results show that the developed flapper-nozzle valve achieves a true diodic flow characteristic.

• Journal of the Microelectronics and Packaging Society
• /
• v.23 no.4
• /
• pp.31-34
• /
• 2016

System In Package (SiP) is getting popular and momentum for the recent wearable, IoT and connectivity application apart from mobile phone. This is driven by market demands of cost competitive, lighter and smaller/thinner and higher performance. As one of many semiconducting assembly products, Leadframe product has been widely used for low cost solution, light/ small and thin form factor. But It has not been applied for SiP although Leadframe product has many advantages in cost, size and reliability performance. SiP is mostly based on laminate substrate and technically difficult on Leadframe substrate because of a limitation in SMT performance. In this paper, Leadframe based SiP product has been evaluated about key technical challenges in SMT performance and electrical shield technology. Mostly Leadframe is considered not available to apply EMI shield because of tie-bar around package edge. In order to overcome two major challenges, connection bars were deployed properly for SMT pad to pad and additional back-side etching was implemented after molding process to achieve electrical isolation from outer shield coating. This product was confirmed assembly workability as well as reliability.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2003.03a
• /
• pp.56-56
• /
• 2003

최근 정보통신 분야의 급격한 발달로 인하여 무선통신에 사용되는 주파수 영역 또한 계속 높아짐에 따라 대역통과 필터 소자의 삽입 손실, 소비 전력, 크기, MMIC화에 대한 많은 연구가 진행되고 있다 압전 현상을 이용한 박막형 공진기가 이러한 요구를 충족시키고, 현재의 SAW filter를 대체할 소자로 떠오르고 있다. 본 실험에서는 단결정 미세 구조를 만들 수 있고, 압전 효과 또한 우수하며, Surface Micromachining보다 비교적 제조 공정이 간단하고 선택적 에칭이 가능한 Bulk Micromachining을 이용하여 Si$_3$N$_4$ Membrane을 이용한 중심주파수 5.2GHz인 두께 진동모드 Film Bulk Acoustic Wave Resonator(FBAR)를 제작하고 공진기의 고주파 특성을 평가하였다. Membrane구조 형성을 위해 Backside면인 Si$_3$N$_4$, Si은 RIE(Reactive Ion Etching)와 선택적 에칭용액인 KOH로 각각 에칭하여 Membrane을 갖는 구조로 중심주파수 5.2GHz인 두께 진동모드 FBAR를 설계 및 제조하였다. 체적 탄성파 공진 현상은 r.f Magnetron Sputtering법으로 증착한 AIN 압전박막과 Mo전극으로부터 발생 가능하였다. 본 연구에서는 0.9$\mu\textrm{m}$-Si$_3$N$_4$ Membrane을 이용해 FBAR를 제작/평가하고, RIE을 통해 Membrane을 제거해 가면서 공진기의 특성 즉, Quality factor와 유효전기기계결합계수(K$_{eff}$) 및 S parameter특성을 비교 측정해 보았다. 측정해본 결과 Membrane Free일때가 훨씬더 공진 특성이 우수함을 볼 수 있다

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.31 no.4
• /
• pp.417-424
• /
• 2007

This paper reports fabrication and characterization of a pressure sensor using a pitch-based carbon fiber. Pitch-based carbon fibers have been shown to exhibit the piezoresistive effect, in which the electric resistance of the carbon fiber changes under mechanical deformation. The main structure of pressure sensors was built by performing backside etching on a SOI wafer and creating a suspended square membrane on the front side. An AC electric field which causes dielectrophoresis was used for the alignment and deposition of a carbon fiber across the microscale gap between two electrodes on the membrane. The fabricated pressure sensors were tested by applying static pressure to the membrane and measuring the resistance change of the carbon fiber. The resistance change of carbon fibers clearly shows linear response to the applied pressure and the calculated sensitivities of pressure sensors are $0.25{\sim}0.35 and 61.8 ${\Omega}/k{\Omega}{\cdot}bar$ for thicker and thinner membrane, respectively. All these observations demonstrated the possibilities of carbon fiber-based pressure sensors.

• Transactions on Electrical and Electronic Materials
• /
• v.3 no.1
• /
• pp.4-8
• /
• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.252-255
• /
• 2004

반도체는 high integrated, high speed, low power를 위하여 design 뿐만 아니라 재료 측면에서도 많은 변화를 가져오고 있으며, RC delay time을 줄이기 위하여 Al 배선보다 비저항이 낮은 Cu와 low-k material 적용이 그 대표적인 예이다. 그러나, Cu 배선의 경우 dry etching이 어려우므로, 기존의 공정으로는 그 한계를 가지므로 damascene 또는 dual damascene 공정이 소개, 적용되고 있다. Damascene 공정은 절연막에 photo와 RIE 공정을 이용하여 trench를 형성시킨 후 electrochemical plating 공정을 이용하여 trench에 Cu를 filling 시킨다. 이후 CMP 공정을 이용하여 절연막 위의 Cu와 barrier material을 제거함으로서 Cu 배선을 형성하게 된다. Dual damascene 공정은 trench와 via를 동시에 형성시키는 기술로 현재 대부분의 Cu 배선 공정에 적용되고 있다. Cu CMP는 기존의 metal CMP와 마찬가지로 oxidizer를 이용한 Cu film의 화학반응과 연마 입자의 기계가공이 기본 메커니즘이다. Cu CMP에서 backside pressure 영향이 uniformity에 미치는 영향을 살펴보았으며, electrochemical plating 공정에서 발생하는 hump가 CMP 결과에 미치는 영향과 dishing 결과를 통하여 그 영향을 평가하였다.