• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.10a
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• pp.307-310
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• 2001

In this paper we describe the design and implementation of uplink receiver for BWLL base station modem. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we use Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.1

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.4
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• pp.323-330
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• 2002

In this paper, we have designed and fabricated an BWLL MMIC amplifier using GaAs PHEMT devices. We have optimized power divider/combiner size for small size of MMIC amplifier Using 0.2 ${\mu}$m AIGaAs/lnGaAs/GaAs PHEMT devices, the two stave MMIC amplifier has demonstrated a S$_{21}$ gain of 8.7 ㏈ with input/output return losses of lower than -10 ㏈ at 26.7 GHz. The size of this chip is 4.11 ${\times}$ 2.66 $\textrm{mm}^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1219-1225
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• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2000.11a
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• pp.179-182
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• 2000

BWLL용 Ka-Band MMIC 저잡음 증폭기 칩을 InGaAs/GaAs 0.15um Gate 길이의 p-HEMT 공정을 이용하여 개발하였다. 칩 크기 2.5$\times$1.5$\textrm{mm}^2$의 2단으로 설계된 칩의 On-wafer 측정 결과, 24～27 GHz BWLL 주파수 대역에서 최소 19$\pm$0.2dB 이득과 최대 1.7dB의 잡음 지수와 최소 13dB의 반사손실의 특성을 얻었다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.71-76
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• 2001

A Ka Band 3-stage MMIC (Monolithic Microwave Integrated Circuits) LNA (Low Noise Amplifiers) has been designed and fabricated far the Ka band satellite communications and BWLL(Broad Band Wireless Local Loop)system. The MMIC LNA consists of two single-ended type amplification stages and one balanced type amplification stage to satisfy noise figure, high gain and amplitude linearity. The 0.15${\mu}{\textrm}{m}$ pHEMT has been used to provide a ultra low noise figure and high gain amplification. Series and Shunt feedback circuits and λ/4 short lines were inserted to ensure high stability over the frequency range form DC to 80 GHz. The size of the MMIC LNA is 3.1mm$\times$2.4mm(7.44mm$^2$). The on wafer measured performance of the MMIC LNA, which agreed with the designed performance, showed the noise figure of less than 2.0 dB, and the gain of more than 26 dB, over frequency ranges from 22 GHz to 30 GHz.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.2
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• pp.63-70
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• 2000

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3C
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• pp.234-240
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• 2002

A power amplifier with AlGaAs/InGaAs/GaAs HBT's has been developed for customer premise equipments of the quasi millimeter-wave frequency-band broadband wireless local loop(BWLL) system. Parameters of the linear and nonlinear equivalent circuits for a common base HBT have been extracted by a fitting method. The amplifier has been designed through the linear and nonlinear circuit simulations and fabricated on a ceramic substrate for a hybrid IC. The amplifier has produced a 25.5-dBm output power with 35% power-added efficiency(PAE) at 24.4 GHz and achieved a 7.5-dB linear power gain at 24.8 GHz. In 24.25 ∼24.75 GHz band, the amplifier has exhibited a saturated output over larger than 22 dBm and PAE higher than 25%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.6
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• pp.959-968
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• 2000

In this paper, a low phase noise frequency synthesizer used to TX local oscillator in BWLL RF tranceiver is presented. The phase-locked stable 25GHz-band frequencies in BWLL TX LO are obtained by using 2 GHz baseband frequency synthesizer, sixth-harmonic frequency multiplier and frequency doubler at 12 GHz band frequency input. The 25 GHz band frequency synthesizer presented in this paper has 3-output frequencies at 24.92 GHz, 25.10 GHz, 25.26 GHz. At 24.92 GHz frequency the synthesizer has 0.44 dBm output power and shows -87.93 dBc/Hz(a 10 KHz), -109.54 dBc/Hz (a100 KHz) phase noise characteristics .

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.837-840
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• 2001

주파수 추정 알고리즘의 경우 기존에 제안된 방법들 중에서 ML방법은 계산상 너무 복잡하고 구현하기 힘들며, 준-ML 방법들은 이론적인 방법과 비교해 볼 때 다소 단순하긴 하나 역시 구현상의 문제가 따른다. 따라서 본 논문에서는 BWLL환경에 적용할 수 있는 단순하면서도 구현이 용이한 주파수 추정방법을 제안한다. 본 논문에서 제안하는 주파수 추정기는 V&V 위상추정기를 기초로 한다. 성능분석 결과 본 논문에서 제안한 알고리즘을 이용할 경우 최대로 정규화된 심벌율의 0.5%까지 조정이 가능하다. 따라서 아날로그 영역에서의 거친 주파수 조절과정에서 다소 많은 잔류 주파수옵셋이 존재하여도 주파수 복구가 가능하다.

• Electronics and Telecommunications Trends
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• v.15 no.6 s.66
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• pp.45-55
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• 2000

현재 국가별로 진행되고 있는 가입자 접속의 고속화 전략은 각 나라의 통신환경 및 서비스 수요에 따라 다양하게 추진되고 있다. 그러나 선로의 종류에 따라 구분하여 보면, 기존의 동선 전화선로를 이용하는 ‘ xDSL 접속’과 새로운 광섬유 선로를 이용하는 ‘광 가입자 접속,’ 그리고 무선주파수를 이용하는 ‘광대역 무선 접속(BWLL)’ 등 세 가지 형태로 구분할 수 있다. 본 고는 이러한 초고속 가입자 접속기술 중 xDSL기술의 개발현황과 표준화 진행을 분석하여 우리나라의 통신환경에 맞는 기술 방향을 제시하고자 한다.