• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
• /
• pp.137-137
• /
• 2006

본 연구에서는 FeRAM 적용을 위한 BLT 캐패시터 제조시 CMP 공정압력 변화에 따른 Leakage Current의 특성에 대해서 연구하였다. 6-inch Pt/Ti/Si 웨이퍼를 사용하였으며, 기판 위에 졸-겔(Sol-Gel)법으로 모든 BLT를 스핀코팅을 이용하여 증착시켰다. 증착된 BLT는 $200^{\circ}C$에서 기본 열처리 후 다시 $700^{\circ}C$에서 후속 열처리 하였다. 이러한 과정을 두번 반복하였며, FeRAM 적용을 위한 BLT 캐패시터 제조시 CMP 공정 중 압력 변화를 달리하여 BLT 캐패시터를 제조한 후 Leakage Current를 측정하였다. 결과적으로 CMP 공정 시 압력의 증가에 따라 Leakage Current값이 증가하였다. CMP 공정시 압력과 박막 표면의 스크레치로 증가로 인해 Leakage Current의 증가하였다고 판단된다.

• Bulletin of the Korean Chemical Society
• /
• 제28권6호
• /
• pp.1005-1009
• /
• 2007

Leukotriene B4 (LTB4) is a potent chemoattractant for leukocytes and considered to be an inflammatory mediator. Human BLT2 (hBLT2) is a low-affinity G-protein coupled receptor for LTB4 and mediates pertussis toxin-sensitive chemotactic cell movement. Here, we dissected the interaction between hBLT2 and G-protein alpha subunits using GST fusion proteins containing intracellular regions of hBLT2 and various Gα protein including Gα i1, Gα i2, Gα i3, Gα s1, Gα o1, and Gα z. Among the tested Gα subunits, Gα i3 showed the highest binding to the third intracellular loop region of hBLT2 with a dissociation constant (KD) of 5.0 × 10?6 M. These results suggest that Gα i3 has the highest affinity to hBLT2, and the third intracellular loop region of hBLT2 is the major component for the interaction with Gα i3.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
• /
• pp.236-236
• /
• 2008

(Bi,La)$Ti_3O_{12}$(BLT) thin film is one of the most attractive materials for ferroelectric random access memory (FRAM) applications due to its some excellent properties such as high fatigue endurance, low processing temperature, and large remanent polarization [1-2]. The authors firstly investigated and reported the damascene process of chemical mechanical polishing (CMP) for BLT thin film capacitor on behalf of plasma etching process for fabrication of FRAM [3]. CMP process could prepare the BLT capacitors with the superior process efficiency to the plasma etching process without the well-known problems such as plasma damages and sloped sidewall, which was enough to apply to the fabrication of FRAM [2]. BLT-CMP characteristics showed the typical oxide-CMP characteristics which were related in both pressure and velocity according to Preston's equation and Hernandez's power law [2-4]. Good surface roughness was also obtained for the densification of multilevel memory structure by CMP process [3]. The well prepared BLT capacitors fabricated by CMP process should have the sufficient ferroelectric properties for FRAM; therefore, in this study the electrical properties of the BLT capacitor fabricated by CMP process were analyzed with the process parameters. Especially, the effects of CMP pressure, which had mainly affected the removal rate of BLT thin films [2], on the electrical properties were investigated. In order to check the influences of the pressure in eMP process on the ferroelectric properties of BLT thin films, the electrical test of the BLT capacitors was performed. The polarization-voltage (P-V) characteristics show a decreased the remanent polarization (Pr) value when CMP process was performed with the high pressure. The shape of the hysteresis loop is close to typical loop of BLT thin films in case of the specimen after CMP process with the pressures of 4.9 kPa; however, the shape of the hysteresis loop is not saturated due to high leakage current caused by structural and/or chemical damages in case of the specimen after CMP process with the pressures of 29.4 kPa. The leakage current density obtained with positive bias is one order lower than that with negative bias in case of 29.4 kPa, which was one or two order higher than in case of 4.9 kPa. The high pressure condition was not suitable for the damascene process of BLT thin films due to the defects in electrical properties although the better efficiency of process. by higher removal rate of BLT thin films was obtained with the high pressure of 29.4 kPa in the previous study [2].

• 한국컴퓨터정보학회논문지
• /
• 제19권4호
• /
• pp.35-41
• /
• 2014

본 논문은 소프트웨어 기반의 2D BitBLT 엔진을 pSOS 운영체제에서 구현하는 것을 제안하였으며, 제안된 BitBLT엔진을 환자감시장치에서 동작을 검증하였다. 본 논문에서 제안한 방법의 검증을 위해, 환자감시장치 보드를 기반으로 하는 별도의 프로토 타입 PCB 보드를 제작하고, 동작을 검증하였다. 메인 보드는 ARM9 기반의 CPU로 설계하였으며, 하드웨어 기반의 BitBLT 모듈을 소프트웨어 기반의 모듈로 동작하면서 가중되는 CPU의 부하문제의 해결을 위해 200Mhz 프로세서 대신 400Mhz 프로세서로 변경하였다. 본 논문에서는 환자감시장치에서 GUI를 구현하는데 있어 그래픽 콘트롤러의 핵심요소 중의 하나인 2D BitBLT 모듈을 커널의 디바이스 드라이버로 구현하였다.

• BMB Reports
• /
• 제54권3호
• /
• pp.182-187
• /
• 2021

Leukotriene B4 (LTB4) is a lipid mediator of inflammation that is generated from arachidonic acid via the 5-lipoxygenase pathway. Previous studies have reported that the receptors of LTB4, BLT1, and BLT2 play mediatory roles in the allergic airway inflammation induced by ovalbumin (OVA). However, considering that house dust mites (HDMs) are the most prevalent allergen and well-known risk factor for asthmatic allergies, we are interested in elucidating the contributory roles of BLT1/2 in HDM-induced allergic airway inflammation. Our aim in this study was to investigate whether BLT1/2 play any roles in HDM-induced allergic airway inflammation. In this study, we observed that the levels of ligands for BLT1/2 [LTB4 and 12(S)-HETE (12(S)-hydroxyeicosatetraenoic acid)] were significantly increased in bronchoalveolar lavage fluid (BALF) after HDM challenge. Blockade of BLT1 or BLT2 as well as of 5-lipoxygenase (5-LO) or 12-lipoxygenase (12-LO) markedly suppressed the production of TH2 cytokines (IL-4, IL-5, and IL-13) and alleviated lung inflammation and mucus secretion in an HDM-induced eosinophilic airway-inflammation mouse model. Together, these results indicate that the 5-/12-LO-BLT1/2 cascade plays a role in HDM-induced airway inflammation by mediating the production of TH2 cytokines. Our findings suggest that BLT1/2 may be a potential therapeutic target for patients with HDM-induced allergic asthma.

• 한국전기전자재료학회논문지
• /
• 제16권10호
• /
• pp.865-870
• /
• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 한국세라믹학회지
• /
• 제43권4호
• /
• pp.220-223
• /
• 2006

BLT nanotubes were synthesized by using simple and convenient method template-wetting process. Porous alumina membranes were prepared by 2 step anodic oxidation as the template. To improve wetting properties and make low surface energy, BLT solution was mixed with polymer. Polymer was removed completely during annealing. After completely etching the template in 30 wt% KOH solution, we demonstrate that BLT nanotubes with a diameter of 200 nm can be fabricated. Grain growth process of BLT nanotubes during baking, and furnace annealing was examined by FE-SEM and XRD.

• 전기학회논문지
• /
• 제61권1호
• /
• pp.99-103
• /
• 2012

The electromagnetic topology and the BLT equation has been used as useful techniques to analyze coupling effects of huge devices. But in the case of systems including complex parts, applying the BLT equation can be difficult to manifest the complex parts with analytic solutions. To resolve this problem, a numerical method can be used to parts of the whole system in advance. In this paper, a microstrip line filter is analyzed using the BLT equation combined with numerical solutions. Consequently, achieved graphs from the BLT equation show good agreements with graphs obtained using a numerical method only.

• 한국전기전자재료학회논문지
• /
• 제16권4호
• /
• pp.265-271
• /
• 2003

Ferroelectric lanthanum-substituted Bi$_4$Ti$_3$O$_{12}$(BLT) thin films were fabricated by spin-coating onto a Pt/Ti/SiO$_2$/Si substrate by metalorganic decomposition technique. The grain size in BLT thin films were prepared with controlled by various drying process. The effect of grain size on the crystallization and ferroelectric properties were investigated by x-ray diffraction and field emission scanning electron microscope. The dependence of crystallization and electrical properties are related to the grain size in BLT thin films with different drying temperature. The remanent polarization of BLT thin film increases with the increasing grain size. The value of 2P$_{r}$ and E$_{c}$ of BLT thin film dried at 45$0^{\circ}C$ were 25.9 $\mu$C/$\textrm{cm}^2$ and 85 kV/cm, respectively. The BLT thin film with larger grain size has better fatigue properties. The fatigue properties revealed that small grained film showed more degradation of switching charge than large grained films.lms.s.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
• /
• pp.186-189
• /
• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.