• Journal of the Microelectronics and Packaging Society
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• v.8 no.2
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.04a
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• Korean Journal of Materials Research
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• v.21 no.12
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• pp.650-654
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• 2011

In this paper, the effects of conventional and newly developed elastomer modified underfill materials on the mechanical shock reliability of BGA board assembly were studied for application in mobile electronics. The mechanical shock reliability was evaluated through a three point dynamic bending test proposed by Motorola. The thermal properties of the underfills were measured by a DSC machine. Through the DSC results, the curing condition of the underfills was selected. Two types of underfills showed similar curing behavior. During the dynamic bending reliability test, the strain of the PCB was step increased from 0.2% to 1.5% until the failure circuit was detected at a 50 kHz sampling rate. The dynamic bending reliability of BGA board assembly using elastomer modified underfill was found to be superior to that of conventional underfill. From mechanical and microstructure analyses, the disturbance of crack propagation by the presence of submicron elastomer particles was considered to be mainly responsible for that result rather than the shear strength or elastic modulus of underfill joint.

• Journal of Mechanical Science and Technology
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• v.18 no.2
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• pp.230-239
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• 2004

A compact model approach of a network of spring elements for elastic loading is presented for the thermal deformation analysis of BGA package assembly. High-sensitivity moire interferometry is applied to evaluate and calibrated the model quantitatively. Two ball grid array (BGA) package assemblies are employed for moire experiments. For a package assembly with a small global bending, the spring model can predict the boundary conditions of the critical solder ball excellently well. For a package assembly with a large global bending, however, the relative displacements determined by spring model agree well with that by experiment after accounting for the rigid-body rotation. The shear strain results of the FEM with the input from the calibrated compact spring model agree reasonably well with the experimental data. The results imply that the combined approach of the compact spring model and the local FE analysis is an effective way to predict strains and stresses and to determine solder damage of the critical solder ball.

• Journal of Welding and Joining
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• v.21 no.4
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• pp.25-30
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• 2003

There have been many researches for small scale packages such as CSP, BGA, and Flipchip. Underfill encapsulant technology is one of the latest assembly technologies. The underfill encapsulant could enhance the reliability of the packages by flowing into the gap between die and substrate. In this paper, the effects of underfill packages by both aspects of thermal and mechanical reliabilities are studied. Especially, it is focused to value board-level reliability whether by the underfill is applied or not. First of all, The predicted thermal fatigue lifes of underfilled and no underfilled $\mu$ BGA solder joints are performed by Coffin-Manson's equation and FEA program, ANSYS(version 5.62). Also, the thermal fatigue lifes of $\mu$ BGA solder joints are experimented by thermal cycle test during the temperature, 218K to 423k. Consequently, both experimental and numerical study show that $\mu$ BGA with underfill has over ten times better fatigue lift than $\mu$ BGA without underfill.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.77-86
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• 2008

The reliability of leaded and lead-free solders of BGA type packages on a printed circuit board was investigated by employing the standard drop test and 4-point bending test. Tested solder joints were examined by optical microscopy to identify associated failure mode. Three-dimensional finite element analysis(FEM) with ANSYS Workbench v.11 was carried out to understand the mechanical behavior of solder joints under the influence of bending or drop impact. The results of numerical analysis are in good agreement with those obtained by experiments. Packages in the center of the PCB experienced higher stress than those in the perimeter of the PCB. The solder joints located in the outermost comer of the package suffered from higher stress than those located in center region. In both drop and bending impact tests, the lead-free solder showed better performances than the leaded solders. The numerical analysis results indicated that stress and strain behavior of solder joint were dependent on various effective parameters.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.