• Journal of Welding and Joining
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• v.17 no.6
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• pp.78-83
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• 1999

Solder joint is the weakest part which connects in mechanically and electronically between package body and PCB(Printed Circuit Board). Recently, the reliability of solder joint become the most critical issue in surface mounted technology. The solder joint interconnection between plastic package and PCB is susceptible to shear stress during thermal storage due to the mismatch in coefficient of thermal expansion between plastic package and PCB. A general computational approach to determine the effect of solder joint shape on the fatigue life presented. The thermal fatigue life was estimated from the engelmaier equation which was obtained from the temperature cycling loading($-65^{\circ}C$ to $150^{\circ}C$). As result of the simulation, TSOP structure has the shortest thermal fatigue life and the same structure Copper lead has 2.5 times as much fatigue life as Alloy 42 lead. In BGA structure, fatigue life time extended 80 times when underfill material exists.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.80-80
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• 2000

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.11a
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• pp.35-35
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• 2007

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.98.1-98
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• 1998

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.575-579
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• 2004

Package reliability test was conducted to investigate the effect of solder paste composition at BGA Package. It was found that the shape and size of the phase form are affected by the processing parameters. The material have used to fill in the via was Sn/36Pb/2Ag and Sn/0.75Cu type solder paste. Sn/36Pb/2Ag and Sn/0.75Cu paste were fabricated on Tape-BGA substrates by screen printing process, and via ball mount data were characterized with variations of dwell time of 85 seconds at reflow peak temperature at 22$0^{\circ}C$ or 24$0^{\circ}C$. The test condition was MRT 30 $^{\circ}C$/60 %RH/96 HR. Failures formed of a ball-off in solder paste process were observed by using a Optical Microscope and SEM(Scanning Electron Microscope). It was concluded that intermetallic layer growth played important roles in increasing solder fatigue strength for addition of Ag composition. The degradation of shear strength of solder composition is discussed.

• Proceedings of the KWS Conference
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• 2002.10a
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• pp.463-468
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• 2002

This study investigates the variations of shear force, displacement, and fracture surface with the shear speed and the number of reflows. The experimental data of shear tests indicate that the shear force increases as increasing the number of reflows and the shear speed due to the formation of a kind of intermetallic compound, Ni$_3$Sn$_4$, on Au/Ni/Cu pad, and the work-hardening. However, general trends show that the shear force decreases due to increasing the thickness of the intermetallic compound over 4x reflow. It is observed that the intermetallic compound which is formed between solder and pad increases according to increasing the number of reflows, and the growth rate of the intermetallic compound at central region on the interface is faster than one at edge part. The general tendencies of shear force and displacement with different shear speeds are almost identical as an increase of the number of reflows.

• Journal of the Microelectronics and Packaging Society
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• v.2 no.1
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• pp.59-68
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• 1995

박막제조 기술 및 BGA패캐지를 이용하여 Wellcom 2000 system 소요 OCU Board 의 집적화를 구현하였다. 기존 PCB에 실장되는 소자 일부를 2 Channel BGA 패캐지로 모 듈화한 결과 약 1/6로 소형화시킬수 있었으며 8 Channel의 모율화는 현재 진행중인 다층 구조의 제조 기술 개발과 아울러 BGA 패캐지로 실현이 가능하며 1/10로집접화할수 있음을 알수 있었다. 또한 PCB위에 Bare Chip을 실장하여 Wire Bonding 한 COB를 구현하여 CBGGA의 PCB실장과 함께한 모듈을 형성해 보았다. CBGA패캐지에 Ball Shear Test, In Circuit Test 온도 환경주기시험(TCT) 진동시험을 통하여 신뢰성을 입증하였다. 이때 CBGA의 Coplanarity(3.2%) 증진을 위하여 Ceramic Pad에 선택적인 도금 방식을 개발적용 하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.109-119
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• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.