• Journal of Electrical Engineering and Technology
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• 제12권4호
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• pp.1593-1599
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• 2017

This paper presents a multi-channel light-emitting diode (LED) driver IC with a current-mode current regulator. The proposed current regulator replaces resistors for current sensing with a sequentially controlled single current sensor and a single regulation loop for sensing and regulating all LED channel currents. This minimizes the current mismatch among the LED channels and increases voltage headroom or, equivalently, power efficiency. The proposed LED driver IC was fabricated in a $0.35-{\mu}m$ BCD 60-V high voltage process, and the chip area is $1.06mm^2$. The measured maximum power efficiency is 93.4 % from a 12-V input, and the inter-channel current error is smaller than as low as ${\pm}1.3%$ in overall operating region.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.120-128
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• 2017

This paper describes a neural stimulation system that employs an inductive coupling link to transfer power and data wirelessly. For the reliable data and power delivery, a self-referenced amplitude-shift keying (ASK) demodulator and a wide-range voltage regulator are suggested and implemented in the proposed stimulator system. The prototype fabricated in 0.35 um BCD process successfully transferred 1.2 Kbps data bi-directionally while supplying 4.5 mW power to internal MCU and stimulation block.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.519-520
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• 2008

In this paper, we design and implement the monolithic zero crossing detection power factor correction IC using a high voltage 30V BCD process. The ZCD PFC IC is designed for power applications, such as notebook, LCD monitor, etc. It includes power factor correction function and several protection circuit, regulator, high-voltage high current output drivers. And also, the designed IC has restart timer function which the output pulse is generated if the output signal of IC is not in a 200us. The simulation results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1997년도 춘계학술대회 논문집
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• pp.145-149
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• 1997

A laser mesurement system, a modified Michelson interferometer,which can accurately measure high speed length and position of servomechanisms by detecting a phase shift in the measurement beam using an optical interference was developed. A frequency stabilized laser source and a 20 fold frequency interpolation and digitizing circuit were applied to the system. The refractive index of the ambient air was calibrated through the Edlen's formula. The system achieved a resolution of .lambda./40,16nm, a maximum allowable measurement speed of 600 mm/sec, and a length measurement range of 1500mm. Performance of the system was evaluated on the machining center in short and long length measurements

• 전자공학회논문지D
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• 제34D권3호
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• pp.41-51
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• 1997

In this study, two types of the direct digital frequency synthesizers (DDFS) designed and implemented using 1.0.mu.m CMOS gatearray(SOG) technolgoies are interoduced. To analize the effect of the number of phase bits(L), address data bits(A), and DAC bits (D) on the output spectrums of the DDFSs, the NCO-based BCD-DDFS composed of L=24, A=14, and D=8, and the improved binary-DDFS composed of L=24, A=8, and D=10 have been studied. The chips have been designed with and without a noise shapper to reduce spurious noises due to phase truncation and reduced sine ROM in output spectrum.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 춘계학술대회 논문집
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• pp.27-28
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• 2009

This paper suggests a autonomous linear Li-ion battery charger which can safely distribute power between an external power source(AC adapter, auto adapter, or USB source), battery, and the system load. Depending on an external power source's capability, the charger selects proper charging-mode automatically. The charger IC designed and fabricated on Dongbu HITEC's $0.35{\mu}m$ BCD process with layers of one poly and three metals.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.532-533
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• 2008

연계지역 전력시장 간의 에너지 거래는 전체 전력시장의 사회적 편익을 향상시키기 위해 이루어진다. 기존의 연계지역 전력시장 간시장 최적화 문제를 다루는 중앙처리 접근방식은 경쟁적 전력시장 환경하에서 적합한 모델이 아니다. 본 논문은 연계지역 전력시장 문제를 다루기 위해 보완 라그랑지안 승수 기법(Augmented Lagrangian Relaxation) 기반의 분산처리 최적화 방법을 제시한다. Block Coordinate Descent(BCD) 분산처리 기법이 보완 라그랑지안 승수의 최적화 문제를 분리하기 위해 적용된다. 연계시장 모델을 구현한 사례연구를 통해 제시된 알고리즘의 효용성을 입증한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1020-1021
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• 2015

본 논문에서는 상용전압 AC 220V를 인가전압으로 사용하여 PMIC(Power Management IC)의 구동에 적합한 전압을 인가해주는 Pre-Regulator를 설계하였다. 설계된 Pre-Regulator는 상용전압을 사용하기 때문에 Device의 내압이 700V인 Magnachip $0.35{\mu}m$ BCD 공정을 이용하여 설계되었으며, 회로의 구성은 저전압 입력 보호 기능 및 JFET의 구동 제어를 위한 Under Voltage Lock Out(UVLO)회로, 전압조정기(Regulator)의 기준전압을 생성해주는 밴드갭 기준전압 발생(Bandgap Reference)회로, LDO(Low Drop Out)회로로 구성되어있다.

• Journal of Power Electronics
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• 제17권5호
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• pp.1372-1381
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• 2017

This paper presents a high-side switch driver IC capable of improving the current sensing accuracy and providing reverse battery protection. Power semiconductor switches used to replace relay switches are encumbered by two disadvantages: they are prone to current sensing errors and they require additional external protection circuits for reverse battery protection. The proposed IC integrates a gate driver and current sensing blocks, thus compensating for these two disadvantages with a single IC. A p-sub-based 90-V $0.13-{\mu}m$ bipolar-CMOS-DMOS (BCD) process is used for the design and fabrication of the proposed IC. The current sensing accuracy (error ${\leq}{\pm}5%$ in the range of 0.1 A-6.5 A) and the reverse battery protection features of the proposed IC were experimentally tested and verified.