• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.3
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• pp.11-17
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• 1978

A medium scale integrated circuit, BCD to seven segment decoder/driver is designed and fabricated by employing P-channel metal-oxide-semiconductor technology. The device configuration is specifically designed for a common cathode seven segment LED display unit. The decoder logic is composed of two serially connected read-only-memory matrices and the LED drivers are implemented with wide channel FET's. The fabricated integrated circuit performed successfully with a supply voltage between -7 Volt and -26 Volt and the non-uniformity of the LED segment current is about 10%.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• BMB Reports
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• v.49 no.10
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• pp.572-577
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• 2016

The short gastrulation (sog) shadow enhancer directs early and late sog expression in the neurogenic ectoderm and the ventral midline of the developing Drosophila embryo, respectively. Here, evidence is presented that the sog primary enhancer also has both activities, with the late enhancer activity dependent on the early activity. Computational analyses showed that the sog primary enhancer contains five Dorsal (Dl)-, four Zelda (Zld)-, three Bicoid (Bcd)-, and no Single-minded (Sim)-binding sites. In contrast to many ventral midline enhancers, the primary enhancer can direct lacZ expression in the ventral midline as well as in the neurogenic ectoderm without a canonical Simbinding site. Intriguingly, the impaired transcriptional synergy between Dl and either Zld or Bcd led to aberrant and abolished lacZ expression in the neurogenic ectoderm and in the ventral midline, respectively. These findings suggest that the two enhancer activities of the sog primary enhancer are functionally consolidated and geographically inseparable.

• The Bulletin of The Korean Astronomical Society
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• v.39 no.1
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• pp.44.1-44.1
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• 2014

Blue Compact Dwarf galaxies (BCDs) are systems that recently have experienced the burst of star formation. As one of the causes for active star formation in BCDs, tidal interaction (fly-by or merger) has been suggested. A pair of BCDs, ESO 435-IG20 and ESO 435-IG16 are separated by only ~80 kpc in projection at a similar redshift (at a ~9 Mpc distance), and hence suspected to be a good example of such case. Intergalactic atomic hydrogen gas found in HIPASS survey is also suggestive of this hypothesis. In this study, we probe the HI morphology and kinematics of this BCD pair using ATCA HI data to study detailed interaction history. We investigate various star formation tracers of the pair to study how responsible tidal interaction is for triggering star formation in these galaxies.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.11
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• pp.491-494
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• 2006

In the adder design, reduction of the delay of the carry propagation or ripple is the most important consideration. Previously, it was introduced that, if a redundant number system is adopted, the carry propagation is completely eliminated, with which addition can be done in a constant time, without regarding to the count of the digits of numbers involved in addition. In this paper, a RBCD(Redundant Binary Coded Decimal) is adopted to code 0 to 11, and an efficient and economic carry-free BCD adder is designed.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.271-273
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• 2007

본 논문에서는 TV나 Audio등에 사용되는 2채널 30W급 Class-D amplifier를 동부하이텍의 0.35um BD350BA 공정을 사용하여 디지털 방식의 Class-D amplifier 출력단 구동에 적합하도록 설계하였다. 출력단은 Bootstrap 전원을 사용한 N-N type의 30V LDMOS 내장형이며 각각 $250m{\Omega}$의 턴 온 저항을 갖게 설계 되었다. THD+N 특성개선을 위한 Dead time 및 Delay 조정회로를 내장하였으며 보호회로로는 Over current, Over temperature, UVLO 가 있다.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1349-1351
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• 2005

In this paper discusses isolation driver of single phase AC-DC reversible power converter The reversible power converter driven by binary combination at different transformer winding ratio by BCD code level. It has a advantage that constructs a control system simply and obtain load current of good quality with out filter circuit and free from noise or isolation for lower switching frequency. In this research, study on current type converter and inverter circuit that consist for possibility of AC-DC/BC-AC multi-level reversible converter.

• Bulletin of the Korean Chemical Society
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• v.21 no.2
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• pp.159-160
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• 2000

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.1-6
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• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.1
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• pp.627-633
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• 2015

We designed of a LDO regulator with a OVP and UVLO protection function for a PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. The proposed LDO regulator is designed for low voltage input power protection. Proposed LDO circuit generated fixed 2.5 V from a supply of 3.3V. It was designed with 3.3 V power supply using a $0.35{\mu}m$ CMOS technology. SPICE simulation results showed that the proposed circuit provides 0.713 mV/V line regulation with output 2.5 V ~ 3.9 V and $8.35{\mu}V/mA$ load regulation with load current 0 mA to 40 mA.