• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.21 no.2
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• pp.276-282
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• 2012

This study looked for Mode status of each for fatigue crack growth behavior about the repeat load of mode I and the static load of mode II. The experiment was performed in the state of the repetition frequency of the sine wave 10Hz, the stress ratio 0.1, maximum load 300kg.f, a static load 0, 100, 200, 300kg.f, As the experimental results, in mode of static load, while the load value increases, the crack growth rate is slower as the energy of a crack mixing grows. Mode I and the power mode II get an influence each other in the direction of crack propagation path, but as they eventually get closer to the breaking point of the crack growth, it is dominated by the mode I.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.7-11
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• 2007

In this paper, we proposed the dual-mode stepped impedance ring resonator bandpass filter for MMIC (Microwave Monolithic Integrated Circuit) applications using the dielectric-supported air-gapped microstrip line (DAML). The ring resonator fabricated by surface micromachining technology. This filter consists of a DAML resonator layer and a CPW feed line. The DAML ring resonator is elevated with $10{\mu}m$ height from GaAs substrate surface. This bandpass filter is $1-{\lambda}g$ type stepped impedance ring resonator including dual-mode resonance. From the measurements, we obtained attenuation of over 15 dB and insertion loss of 2.65 dB at the center frequency of 97 GHz. Relative bandwidth is about 12 % at 97 GHz. Furthermore, the proposed bandpass filter is useful to integrate with conventional MMICs.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.313-318
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• 2018

A coaxial band rejection filter is designed and fabricated for a beam interacting cavity. The proposed filter has a quarter wavelength choke for the dominant mode of the cavity. The equivalent circuit of the coaxial band rejection filter is presented and the ABCD parameter os each part is derived to obtain the ABCD parameter of the entire filter. The scattering matrix was obtained from the ABCD matrix and the was simulated by MATLAB using the obtained scattering matrix. The coaxial band rejection filter structure was simulated using HFSS, and the results confirmed the simulation using the equivalent circuit was useful. The designed coaxial band rejection filter was fabricated with 6-1/8 flange. The fabricated filter was measured using a transition from 6-1/8 flange to N-type flange. The insertion loss of the fabricated filter is greater than 25 dB in the dominant mode of the cavity and less than 0.25 dB in the first higher order mode. The measurement results are in good agreement with the simulated results and meet the design specification.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.5
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• pp.1143-1150
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed using a $0.25-\mum$ 5-metal CMOS technology. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles. The DMM consists of a $28-b\times28-b$ single-precision multiplier designed using radix-4 Booth receding and redundant binary (RB) arithmetic, an accumulator and a simple control logic for mode selection. It contains about 25,000 transistors on the area of about $0.77\times0.40-m^2$. The HSPICE simulation results show that the DMM core can safely operate with 200-MHZ clock at 2.5-V, and its estimated power dissipation is about 130-㎽ at double-precision mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.10
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• pp.1052-1059
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• 2003

In this paper, we proposed the directional coupler using two layer microstrip substrate which is improved coupling and isolation. Also, we notified a design method. Modified re-entrant mode coupler is the structure added to the aperture on the ground plane in order to improving the coupling value. And, by adding to slits on the floating conductor, this structure has good performance in isolation, VSWR according to S$\sub$11/, and phase difference. As a result, proposed re-entrant mode microstrip directional coupler has about 1.5 dB more higher coupling and 20 dB more higher isolation than conventional coupler. And because this coupler has good performance in phase difference, it can be used multi-section coupler.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.766-772
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• 2018

A 6~10 GHz wide-band power amplifier was designed using an InGaAs enhancement-mode(E-mode) $0.15{\mu}m$ pseudomorphic high-electron-mobility transistor(pHEMT). The positive gate bias of the E-mode pHEMT device removes the need for complex negative voltage generation circuits, therefore reducing the module size. The wire bond and substrate loss parameters were modeled and extracted using a three-dimensional electromagnetic(3D EM) simulation. For wideband characteristics, lossy matching was adopted and the gate bias was optimized for maximum power and efficiency. The measured gain, in/output return loss, output power, and power-added efficiency were greater than 20 dB, 8 dB, 27 dBm, and 35 %, respectively, in the 6~10 GHz band.

• Journal of Broadcast Engineering
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• v.16 no.3
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• pp.416-426
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• 2011

In this paper, we proposed an intra coding method with merging intra prediction mode to achieve intra coding gain. The proposed method uses signaling of prediction mode with merging prediction modes, which is different from the conventional method. If the number of blocks that has the same prediction mode compared to that to be predicted from neighboring blocks exceeds the predefined threshold, then the proposed method is used in order to reduce bits of intra prediction mode for coding efficiency. Otherwise the conventional method is used. Experimental results show the proposed method achieves the PSNR gain of about 0.05 dB in RD curve and reduces the bit rates about 1 % compared with H.264/AVC. In particular, the PSNR gain of about 0.1 dB in RD curve and reduces the bit rates about 1.7 % compared with H.264/AVC at low bit-rates. we can know that the proposed method is efficient tool at low bit-rates.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.570-582
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• 2012

In the communication, a reconfigurable antenna using two PIN diodes is presented for quad-band(GSM900/GSM1800/GSM1900/UMTS) mobile handset applications. The proposed antenna has a size $45{\times}11{\times}6mm^3$. By independently adjusting the on/off states of two PIN diodes located on the radiating element, the proposed structure can be operated in the PIFA and loop mode, respectively. The PIN diodes are replaced by conducting tape in order to verify the concept. In regards to the fabricated reconfigurable antenna, when operating in the PIFA mode, the measured results show that the 7 dB bandwidth is 8.62 %. which covers the GSM900(880~960 MHz) band. When operating in the loop mode, the measured results show that the 7 dB bandwidth is 26.36 %, which covers the GSM1800(1,710~1,880 MHz), GSM1900(1,850~1,990 MHz), and UMTS(1,920~2,170 MHz) bands, respectively.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.260-264
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• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• Journal of IKEEE
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• v.22 no.4
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• pp.1088-1092
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• 2018

In this paper, we propose a dual-mode frequency tripler using push-push and stacked FET structures. The proposed circuit can operate either in frequency multiplier mode or in amplifier mode. In the frequency multiplier mode, push-push frequency multiplication is achieved by allowing input signals with particular phase shifts. In the amplifier mode, the device operates as a distributed amplifier to obtain high gain. Also both modes were designed using stacked FET structure. The designed circuit showed frequency tripled output power of 9.7 dBm at 2.4 GHz with the input at 800 MHz. On the other hand, in the amplifier mode, the device showed 8.9 dB of gain to generate 19.5 dBm at 800 MHz.