• Korean Journal of Materials Research
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• v.25 no.5
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• pp.233-237
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• 2015

Silicon oxynitride that can be deposited two times faster than general SiNx:H layer was applied to fabricate the passivation protection layer of atomic layer deposition (ALD) $Al_2O_3$. The protection layer is deposited by plasma-enhanced chemical vapor deposition to protect $Al_2O_3$ passivation layer from a high temperature metallization process for contact firing in screen-printed silicon solar cell. In this study, we studied passivation performance of ALD $Al_2O_3$ film as functions of process temperature and RF plasma effect in plasma-enhanced chemical vapor deposition system. $Al_2O_3$/SiON stacks coated at $400^{\circ}C$ showed higher lifetime values in the as-stacked state. In contrast, a high quality $Al_2O_3$/SiON stack was obtained with a plasma power of 400 W and a capping-deposition temperature of $200^{\circ}C$ after the firing process. The best lifetime was achieved with stack films fired at $850^{\circ}C$. These results demonstrated the potential of the $Al_2O_3/SiON$ passivated layer for crystalline silicon solar cells.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.231-231
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• 2010

현재 Cu배선 제조공정에서 전해도금은 Damascene pattern의 Cu filling에 사용되고 있는데, 우수한 특성의 전해도금을 위해서는 step coverage가 우수한 Cu seed layer가 필수적이다. 현재까지 Cu seed layer를 형성하는 방법으로는 ionized physical vapor deposition(I-PVD)이 사용되고 있는데, 22 nm 이후의 소자에서는 step coverage의 한계로 인해 완벽한 Cu filling 어려울 것으로 예상된다. 본 연구에서는 step coverage가 매우 우수한 atomic layer deposition(ALD) 방법으로 Cu seed layer를 증착하고 그 특성을 기존의 PVD 박막과 비교하였다. Ketoiminate 계열의 +2가 Cu 전구체와 $H_2$를 이용하여 ALD Cu 박막을 증착하였는데 exposure, 기판의 온도를 변화시키면서 기판별로 ALD Cu의 최적공정조건을 도출하였다. ALD Cu seed와 PVD Cu seed 위에 약 $1{\mu}m$의 Cu 박막을 전해도금한 후 박막의 두께, 비저항, 미세구조와 함께 pattern filling 특성을 비교하였다.

• Applied Science and Convergence Technology
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• v.23 no.1
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• pp.40-43
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• 2014

We investigated the growth characteristics and interfacial properties of $HfO_2$ films deposited on Ge substrate through atomic layer deposited (ALD) by using an in-situ medium energy ion scattering analysis. The growth kinetics of $HfO_2$ grown on a $GeO_2/Ge$ substrate through ALD is similar to that grown on an $SiO_2/Si$ substrate. However, the incubation period of $HfO_2$ deposition on Ge is shorter than that on Si. The $HfO_2$ grown on the GeO/Ge substrate shows a significant diffusion of Hf atoms into the substrate interface and GeO volatilization after annealing at $700^{\circ}C$. The presence of low-quality Ge oxide or suboxide may degrade the electrical performance of device.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.103-104
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• 2015

정확한 두께와 조성 제어, 훌륭한 재현성의 박막을 형성할 수 있는 Atomic layer deposition 방법으로 증착시킨 ZnO 박막은 여러 분야에 적용될 수 있기 때문에 최근 많은 주목을 받고 있다. ALD-ZnO 박막을 형성하기 위하여 가장 흔히 사용되는 전구체 (precursor)와 반응체 (reactant)는 DEZ(DiethylZinc)와 $H_2O$이다. 그러나 DEZ 전구체를 사용한 ALD-ZnO 박막은 낮은 열적 안정성이 문제로 지적되어져 왔으며, 또한 여러 분야의 적용 및 산업화를 위해서는 높은 증착률, 큰 범위의 전기적 저항, 높은 투과도가 필요로 한다. 본 연구에서는 atomic layer deposition 기법을 통해 열적 안정성을 가진 새로운 전구체인 DEZDMEA ($Et_2Zn:NEtMe_2$)을 사용하여 ZnO 박막을 증착하였다. DEZDMEA ($Et_2Zn:NEtMe_2$) 및 $H_2O$ 주입 시간에 따른 증착률와 전기적 성질, 투과도를 조사하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.329-329
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• 2016

Large-area graphene films produced by means of chemical vapor deposition (CVD) are polycrystalline and thus contain numerous grain boundaries that can greatly degrade their performance and produce inhomogeneous properties. A better grain boundary engineering in CVD graphene is essential to realize the full potential of graphene in large-scale applications. Here, we report a defect-selective atomic layer deposition (ALD) for stitching grain boundaries of CVD graphene with ZnO so as to increase the connectivity between grains. In the present ALD process, ZnO with hexagonal wurtzite structure was selectively grown mainly on the defect-rich grain boundaries to produce ZnO-stitched CVD graphene with well-connected grains. For the CVD graphene film after ZnO stitching, the inter-grain mobility is notably improved with only a little change in free carrier density. We also demonstrate how ZnO-stitched CVD graphene can be successfully integrated into wafer-scale arrays of top-gated field effect transistors on 4-inch Si and polymer substrates, revealing remarkable device-to-device uniformity.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.107-108
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• 2007

In order to investigate the electrical properties of Hf-silicate as a function of annealing temperature, Hf-silicate deposited by atomic layer deposition (ALD) was studied. After Hf-silicate film deposition, annealing was proceeded at $500^{\circ}C\;and\;700^{\circ}C$. The hysteresis of C-V curves and trapping charge densities were decreased after annealing process. As annealing temperature became higher from $500^{\circ}C\;to\;700^{\circ}C$, the capacitance equivalent thickness (CET) was increased from 1.66 nm to 1.76 nm and the leakage current at -1 V was decreased from $1.70{\times}10^{-4}\;to\;5.68{\times}10^{-5}\;A/cm^2$.

• Transactions on Electrical and Electronic Materials
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• v.12 no.3
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• pp.127-130
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• 2011

We investigated the effects of $O_2$ annealing (i.e., temperature and time) on the characteristics of hafnium silicate ($HfSi_xO_y$) films deposited on a Si substrate by atomic layer deposition process (ALD). We found that the post deposition annealing under oxidizing ambient causes the oxidation of residual Hf metal components, resulting in the improvement of electrical characteristics (e.g., hysteresis window and leakage current are decreased). In addition, we observed the annealing temperature is more important than the annealing time for post deposition annealing. Based on these observations, we suggest that post deposition annealing under oxidizing ambient is necessary to improve the electrical characteristics of $HfSi_xO_y$ films deposited by ALD. However, the annealing temperature has to be carefully controlled to minimize the regrowth of interfacial oxide, which degrades the value of equivalent oxide thickness.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2015.05a
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• pp.47-47
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• 2015

Atomic layer deposition (ALD) 방법으로 증착시킨 ZnO 기반의 박막물질들을 다양한 종류의 태양전지에서 TCO, Buffer Layer 등으로 활용하기 위한 노력이 최근 이루어지고 있다. 본 발표에서는 ALD를 이용한 ZnO 기반 박막물질들의 광전소자로의 적용을 위한 요구물성을 맞추기 위한 precursor/reactant의 selection을 포함한 공정 parameter가 박막의 물성에 미치는 영향 및 생산성 향상을 위한 ALD 공정장치 개발 예를 소개하고, 광전소자 특성에 미치는 영향을 살펴보았다.

• Korean Journal of Optics and Photonics
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• v.35 no.4
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• pp.175-183
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• 2024

Research into optical signal processing using photonic integrated circuits (PICs) has been actively pursued in various fields, including optical communication, optical sensors, and quantum optics. Among the materials used in PIC fabrication, polymers have attracted significant interest due to their unique characteristics. To fabricate polymer-based PICs, establishing an accurate manufacturing process for the cross-sectional structure of an optical waveguide is crucial. For stable device performance and high yield in mass production, a process with high reproducibility and a wide tolerance for variation is necessary. This study proposes an efficient method for fabricating polymer optical-waveguide devices by introducing the atomic layer deposition (ALD) process. Compared to conventional photoresist or metal-film deposition methods, the ALD process enables more precise fabrication of the optical waveguide's core structure. Polyimide optical waveguides with a core size of 1.8 × 1.6 ㎛² are fabricated using the ALD process, and their propagation losses are measured. Additionally, a multimode interference (MMI) optical-waveguide power-splitter device is fabricated and characterized. Throughout the fabrication, no cracking issues are observed in the etching-mask layer, the vertical profiles of the waveguide patterns are excellent, and the propagation loss is below 1.5 dB/cm. These results confirm that the ALD process is a suitable method for the mass production of high-quality polymer photonic devices.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.57-57
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• 2018

Zinc-oxide (ZnO), II-VI semiconductor with a wide and direct band gap (Eg: 3.2~3.4 eV), is one of the most potential candidates to substitute for ITO due to its excellent chemical, thermal stability, specific electrical and optoelectronic property. However, the electrical resistivity of un-doped ZnO is not low enough for the practical applications. Therefore, a number of doped ZnO films have been extensively studied for improving the electrical conductivities. In this study, Ti-doped ZnO films were successfully prepared by atomic layer deposition (ALD) techniques. ALD technique was adopted to careful control of Ti doping concentration in ZnO films and to show its feasible application for 3D nanostructured TCO layers. Here, the structural, optical and electrical properties of the Ti-doped ZnO depending on the Ti doping concentration were systematically presented. Also, we presented 3D nanostructured Ti-doped ZnO layer by combining ALD and nanotemplate processes.