• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3152-3159
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• 2012

This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.

• International Journal of Contents
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• v.5 no.2
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• pp.53-58
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• 2009

This paper presents a novel approach in the design of a CAM for an asynchronous cache. The architecture of cache mainly consists of four units: control logics, content addressable memory, completion signal logic units and instruction memory. The pseudo-DCVSL is useful to make a completion signal which is a reference for handshake control. The proposed CAM is a very simple extension of the basic circuitry that makes a completion signal based on DI model. The cache has 2.75KB CAM for 8KB instruction memory. We designed and simulated the proposed asynchronous cache including CAM. The results show that the cache hit ratio is up to 95% based on pseudo-LRU replacement policy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of Industrial Convergence
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• v.20 no.7
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• pp.37-50
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• 2022

This study intends to analyze the learning effect of asynchronous online classes used in education fields around the world after the COVID-19 pandemic. To this end, we compared and analyzed the lecture evaluation and final exam questions of the HTML5 web programming course, which was conducted offline in 2019 and asynchronously online in 2020 due to COVID-19. As a result of the analysis, no significant difference was drawn between the two teaching methods in the lecture evaluation score and final exam score. However, contrary to concerns about the application of online classes to the entire curriculum, the lecture evaluation and final exam scores of the video-based online classes were high, suggesting the possibility that online classes could be more effective than offline classes if well organized and managed in the future.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• Asia pacific journal of information systems
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• v.22 no.1
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• pp.1-27
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• 2012

Asynchronous Learning Networks (ALN) has become a kind of prevalent information systems to supplement or even substitute a traditional classroom face-to-face teaching method. In this paper, we investigate the impacts of types of courses, lecturers' instruction models and computer self-efficacy on the ALN effectiveness in teaching from lecturers' perspective. We conducted survey to professors in various faculties such as School of Computing, Faculty of Arts, Science, Business, Law and Engineering in the National University of Singapore. According to the responses from ninety-eight professors, instruction modes positively influence the usage of ALN; types of course and lecturers' computer-efficacy influence lectures' satisfaction of ALN in teaching. Both the usage of ALN and satisfaction of ALN positively influence the effectiveness of ALN. The results of this study fill the gap of ALN researches in education by examining it from lecturers' perspective and enable schools to improve their implementation of ALN systems based on our findings.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Journal of Information Science Theory and Practice
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• v.6 no.1
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• pp.45-64
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• 2018

The global information economy is transforming the way people connect with each other, learn new things, and contribute to the knowledge society. With the online platform, library services have also expanded beyond face to face interaction. Although studies of virtual reference services have been made in different parts of the world, a case study discussing various forms of online reference engagement in Kazakhstan has not been written. While most of the theories on connectivism emphasize the context of instruction, the researchers of this paper discussed the tenets as they relate to online engagement. Applying the theory of connectivism, this paper explores through a mixed method the use of various online platforms to enhance engagement connecting library users to information. Findings revealed that differences in patterns of interactions as to platforms, types of queries, and users reveal that students, faculty, and other members of the academic community served by the library have various preferences for communication. The case study further showed that respondents have not maximized the use of VLS but interest in using both synchronous and asynchronous services is clear. Finding connections between sources of information, creating useful information patterns, is essential in learning. Amplifying awareness on the use of VLS giving emphasis to the unique features of each service is useful in order to enable students to see how this platform facilitates learning.

• International Journal of Contents
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• v.12 no.2
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• pp.49-57
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• 2016

This paper aims to explore instructional design of a cyber classroom for secondary students' basic English language competence. A paucity of support for low or under achieving students' English learning exists particularly at the secondary level. In order to bridge the gap, there has been demand for online educational resources considered to be an effective tool in improving students' self-directed learning and motivation. This study employs a comprehensive approach to instructional design for the asynchronous cyber classroom with the underlying premise that different learning theories can be applied in a complementary manner to serve different pedagogical purposes best. Gagné's conditions of learning theory, Bruner's constructivist theory, Carroll's minimalist theory, and Vygotsky's social cognitive development theory serve as the basis for designing instruction and selecting appropriate media. The ADDIE model is used to develop online teaching and learning materials. Twenty-five key grammatical features were selected through the analysis of the national curriculum of English, being grouped into five units. Each feature is covered in one cyber asynchronous class. An Integration Class is given at the end of every five classes for synthesis, where students can practice grammatical features in a communicative context. Related theories, pedagogical practices, and practical web-design strategies for cyber Basic English classes are discussed with suggestions for research, practice and policy to support self-directed learning through a cyber class.