• 전자공학회논문지A
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• 제33A권10호
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• pp.195-204
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• 1996

We suggest a transform method form asynchronous finite state machines (AFSMs) into signal transition graphs (STGs) for speed-independent circuit synthesis. Existing works synthesize nodes in the state graph increases exponentially as the number of input and output signals increases. To overcome the problem of the exponential data complexity, we transform AFSMs into STGs so that the previous synthesis algorihtm form STGs can be applied.Accoridng to the experimental results, it turns out that our synthesis method produces more efficient circuit than the previous synthesis methods.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.349-352
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• 2001

As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.733-736
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• 1999

In this Paper, Bit selectable and Bi-directional Interface Port is described, which can communicate data with the peripheral devices. Specially A description of the asynchronous design method is given to remove the clock skew phenomenon and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.5㎱.

• 디지털산업정보학회논문지
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• 제5권2호
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• pp.39-49
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• 2009

In this paper, we classify web-based social network into two types: open and community, and model user behavior in social activities. After that, we also propose the combination of instant messaging and web system as the method of support asynchronous/synchronous social activities. Furthermore, we introduce ImCoWeb prototype system that supports both asynchronous social activities (ex. social bookmark, comment, rate, and data share) and synchronous ones (ex. real-time communication, file transfer, co-browsing, and co-work). Because it is built on the existing instant messaging, it reduces costs by reusing the facilities such as session management, user management, and security of instant messaging.

• 정보처리학회논문지A
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• 제11A권1호
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• pp.67-74
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• 2004

대부분의 병렬 알고리즘은 동기 알고리즘으로, 올바른 계산을 위해 작업을 일찍 끝낸 빠른 프로세서들은 동기점에서 느린 프로세서를 기다려야 하는데, 프로세서들의 성능이 다를 경우 연산 속도는 가장 느린 프로세서에 의해 결정된다. 본 논문에서는 거대 고유치 문제의 주요 고유쌍을 구하는 문제에 있어서 빠른 프로세서의 유휴 시간을 줄여 수렴 속도를 가속한 수 있는 동기/비동기 혼합 알고리즘을 고안하고 이를 MPMD 프로그래밍 방식을 사용하여 구현하였다.

• 정보처리학회논문지A
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• 제12A권5호
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• pp.421-426
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• 2005

대규모 병렬 연산에 있어서, 계산 노드 혹은 이들을 연결한 통신 네트워크의 장애는 연산 실패로 끝나며, 소중한 계산 시간이 낭비된다. 그러나 현재의 MPI 표준은 이에 대한 대안을 제시하지 않고 있다. 본 논문에서는, 비표준의 무정지형 MPI 라이브러리가 아닌 MPI 표준 함수들만을 사용하여, MPMD 방식의 비동기 연산을 도입한 응용 수준의 무정지형 선형 시스템의 해법을 제안한다.

• ETRI Journal
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• 제28권6호
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• pp.709-720
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• 2006

In this paper, we suggest a simple and efficient multiple-forwarder-based file distribution method which can work with a tree-based application layer multicast. Existing multiple-forwarder approaches require high control overhead. The proposed method exploits the assumption that receivers join a session at different times. In tree-based application layer multicast, a set of data packets is delivered from its parent after a receiver has joined but before the next receiver joins without overlapping that of other receivers. The proposed method selects forwarders from among the preceding receivers and the forwarder forwards data packets from the non-overlapping data packet set. Three variations of forwarder selection algorithms are proposed. The impact of the proposed algorithms is evaluated using numerical analysis. A performance evaluation using PlanetLab, a global area overlay testbed, shows that the proposed method enhances throughput while maintaining the data packet duplication ratio and control overhead significantly lower than the existing method, Bullet.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2010년도 추계학술대회
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• pp.427-430
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• 2010

MOST Network는 오디오와 비디오 데이터를 실시간으로 전송하는 동기식데이터 영역과 패킷데이터를 전송하는 비동기식 데이터 영역, 네트워크 관리를 위한 명령, 상태, 진단 정보를 전송하는 control Channel로 구성되어 있다. 본 논문에서는 비동기식 데이터 영역과 Control Channel의 데이터를 캡처 및 분석하는 모듈을 설계 및 구현한 후 실제 MOST 네트워크를 구축하여 검증해 보았다. 구현한 시스템을 바탕으로 고가의 장비를 별도로 보유하지 않더라도 MOST Network의 비동기식 데이터 영역과 Control Channel의 데이터를 확인할 수 있으며, 분석이 가능한 시스템을 제안하였다.

• ETRI Journal
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• 제39권4호
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.