• Journal of Information Processing Systems
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• v.9 no.4
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• pp.567-574
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• 2013

In this paper, we have proposed an architectural solution for a system for the visualization and modification of large amounts of data. The pattern is based on an asynchronous execution of programmable commands and a reflective approach of an object structure composition. The described pattern provides great flexibility, which helps adopting it easily to custom application needs. We have implemented a system based on the described pattern. The implemented system presents an innovative approach for a dynamic data object initialization and a flexible system for asynchronous interaction with data sources. We believe that this system can help software developers increase the quality and the production speed of their software products.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.410-424
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• 1993

In this paper, we present new techniques for designing systolic arrya and asynchronous arrays for digital-signal processings. More specifically, we propose a systolic array with simple local interconnections which achieves optimal performance without having undesirable features such as preloading input data or global broadcasting. As asynchronous array for digital-signal processings, which can speed up the total computation time significantly is also which can speed up the total computation time significantly is also presented. The key component of the asynchronous array is a presented. The key component of the asynchronous array is a comunicaiton protocol which controls input data flow properly and efficiently. Finally, performance of the arrays is analyzed and a simulation using Occam programmed in a Transputer network is reported.

• Journal of IKEEE
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• v.22 no.3
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.466-471
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• 2014

An asynchronous optical packet-switching (AOPS) node with load-balancing capability can achieve better performance in reducing the high packet-loss ratio (PLR) and time delay caused by unbalanced traffic. This paper proposes a novel dynamic load-balancing algorithm for an AOPS node with limited buffer and without wavelength converters, and considering the data flow distribution and service levels. By calculating the occupancy state of the output ports, load state of the input ports, and priorities for data flow, the traffic is balanced accordingly. Simulations demonstrate that asynchronous variant data packets and output traffic can be automatically balanced according to service levels and the data flow distribution. A PLR of less than 0.01% can be achieved, as well as an average time delay of less than 0.46 ns.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.141-144
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• 2000

In this paper, a new parallel array structure for the asynchronous array multiplier is introduced. This structure is designed for a data dependent asynchronous multiplier to reduces power which is wasted in conventional array structure. Simulation shows that this structure saves 30％ of power and 55％ of computation time comparing to conventional booth encoded array multiplier.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.415-417
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• 2005

Core operations (e.9. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronization. Our Paper mingles the scheme of dynamic clustering and diffusion based asynchronous averaging algorithm for clock synchronization in sensor network. Our proposed algorithm takes the advantage of dynamic clustering and then applies asynchronous averaging algorithm for synchronization to reduce number of rounds and operations required for converging time which in turn save energy significantly than energy required in diffusion based asynchronous averaging algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.12
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• pp.873-875
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• 2014

In this paper we describe an asynchronous MAC protocol with receiver-initiated duty cycling for energy-efficiency in wireless sensor networks(WSN). Legacy asynchronous MAC protocols, X-MAC and PW-MAC, has weaknesses which generates too many control packets and has data collision problem between multiple transmitters, respectively. Therefore, we propose a receiver-initiated asynchronous MAC protocol which generates control packets from transmitter to complement these disadvantages. Compared to the prior asynchronous duty cycling approaches of X-MAC and PW-MAC, the proposed protocol shows a improvement in energy-efficiency, throughput and latency from simulation results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.