• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.38-48
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• 1998

Generating test patterns for asynchronous sequential circuits remains to be a very difficult problem. There are few algorithms for this problem, and previous works cut feedback loops, and insert synchronous flip-flops in the feedback loops during ATPG. The conventional algorithms are similar to the algorithms for synchronous sequential circuits. This means that the conventional algorithms generate test patterns by modeling asynchronous sequential circuits as synchronous sequential circuits. So, test patterns generated by those algorithms nay not detect target faults when the test patterns are applied to the asynchronous sequential circuit under test. In this paper an algorithm is presented to generate test patterns for asynchronous sequential circuits. Test patterns generated by the algorithm can detect target faults for asynchronous sequential circuits with the minimal possibility of critical race problem and oscillation. And it is guaranteed that the test patterns generated by the algorithm will detect target faults.

• Journal of Electrical Engineering and Technology
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• v.12 no.3
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• pp.1090-1100
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• 2017

This paper presents the comparison of starting current characteristics of a three-phase induction motor fed by two types of soft starters. The first soft starter under investigation is a conventional AC voltage controller on the basis of a phase-control technique. The other is the proposed asynchronous PWM AC chopper which is developed from the conventional synchronous PWM AC chopper. In this paper, the proposed asynchronous PWM AC chopper control scheme is developed by generating only two asynchronous PWM signals for a three-phase main power circuit (6 switching devices) from a single voltage control signal which is compared with a single sawtooth carrier signal. By this approach, the PWM signals are independent and easy to implement since the PWM signals do not need to be synchronized with a three-phase voltage source. Details of both soft starters are discussed. The experimental and simulation results of the starting currents are shown. It is found that the asynchronous PWM AC chopper efficiently works as a suitable soft starter for the three-phase induction motor due to that the starting currents are reduced and are sinusoidal with less harmonic contents, when being compared with the starting current waveforms using the conventional phase-control starting technique. Also the proposed soft starter offers low starting electromagnetic torque pulsation.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.983-984
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• 2011

An effective estimation method of equivalent circuit parameters of three-phase induction motor by using FEM is presented in this paper. Arbitrary three torque-speed points at asynchronous speed on the torque-speed curve are required by using time-stepping FEM, then the equivalent circuit parameters of IM can be calculated rapidly with presented method. After obtaining the equivalent circuit parameters, the general analysis method based on equivalent circuit can be used to get entire torque-speed curve very quickly. Although the purely numerical method such as FEM also can estimate torque-speed curve directly and accurately, however, usually this process is time consuming.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.287-290
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• 1990

The paper describes the correction of the switching dead times avoiding a bridge leg short circuit in pulse width modulated voltage sorce inverters. The co consequences on AC variable speed drives with synchronous and asynchronous motors are described by harmonic analysis and by computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Journal of Power Electronics
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• v.14 no.3
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• pp.413-420
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• 2014

The conventional Phase-Shift Full-Bridge (PSFB) converter has a serious voltage spike because of the ringing between the leakage inductance of the transformer and the parasitic output capacitance of the secondary side rectifier switches. To overcome this problem, an asynchronous active clamp technique employing an auxiliary DC/DC converter has been proposed. However, an exact analyses for designing the auxiliary DC/DC converter has not been presented. Therefore, the amount of power that is supposed to be handled in the auxiliary DC/DC converter is calculated through a precise mode analyses in this paper. In addition, this paper proposes a lossy snubber circuit with hysteresis characteristics to reduce the burden that the auxiliary DC/DC converter should take during the starting interval. This technique results in optimizing the size of the magnetic component of the auxiliary DC/DC converter. The operational principles and the theoretical analyses are validated through experiments with a 48V-to-30V/15A prototype.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.96-102
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• 2014

In this paper, we proposed new dual-rail data encoding that mixed 4-phase handshaking protocol and 2-phase handshaking protocol for asynchronous system design to reduce signal activities and power consumption. The dual-rail data encoding 4-phase handshaking protocol should leat to much signal activities and power consumption by return to space state. Ideally, the dual-rail data encoding 2-phase handshaking protocol should lead to faster circuits and lower power consumption than the dual-rail 4-phase handshaking protocol, but can not designed using standard library. We use a benchmark circuit that contains a multiplier block, an adder block, and latches to evaluate the proposed dual-rail data encoding. The benchmark circuit using the proposed dual-rail data encoding shows an over 35% reduction in power consumption with 4-phase dual-rail data encoding.

• Journal of the Korean Institute of Intelligent Systems
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• v.26 no.2
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• pp.135-140
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• 2016

Corrective controllers enable fault diagnosis and tolerance for various faults in asynchronous sequential circuits without resort to redesign. In this paper, we propose a static corrective controller in order to decrease the size of the controller. Compared with dynamic controllers, static controllers can be made using only combinational circuits, as they need no inner states. We address the existence condition and design procedures for static corrective controllers that overcome state transition faults. To show the validity and advantage, the proposed controller is applied to an SEU error counter implemented on FPGA.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• Electronics and Telecommunications Trends
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• v.30 no.6
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• pp.90-98
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• 2015

본 논문에서는 비동기식 회로기술의 최근 동향을 분석하기 위해 관련 분야의 가장 저명한 학회인 비동기식 회로 및 시스템 학회(International Symposium on Asynchronous Circuits and Systems: ASYNC)에 투고된 논문과 기존의 동향분석 자료를 비교 분석하여 제시하고, 관련 업체의 상용화 사례를 통한 비동기식 회로 기술전망을 제시한다. 조사된 논문은 2011년부터 2015년까지 투고된 총 90편의 논문을 각 기준에 따라 분류하고, 연도별, 국가별, 기관별 동향을 분석함으로 최근 관련 기술의 연구동향을 통계화하여 제시하였다. 분석 결과 지난 최근 3년 내 Low Power 분야가 주목할 만한 성장세를 보였고, 상용화 사례로는 Intel의 비동기식 설계를 통한 네트워크 칩, IBM의 Brain inspired processor인 TrueNorth 프로세서 등이 주목할 만하다.