• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.4
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• pp.326-334
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• 1991

We propose an optical Asynchronous Transfer Mode(ATM) switching system using free-space optics and an output buffer memory. The distributor system in the switching fabric was analyzed using the Huygens-Fresnel principle and lens transformation. For monochromatic illumination, a pattern similar to the Fourier transform of the input distribution was observed across the output plane. A spatially broadened intensity distribution across the the output plane can be expected when the system is illminated with a partially coherent, quasimonochromatic beam. Spatially coherent pulses as short as 100fs can propagate through the distributor without severe spatial broadening.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.11
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• pp.47-52
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• 2015

This paper derives the problems that occur when asynchronous transfer in case of phase, frequency, voltage between the emergency generator and the grid and proposed the countermeasure to solve this problem when the transfer switch replace ATS(Automatic Transfer Switch) with CTTS(Closed Transition Transfer Switch) for the non-interrupting switching. In order to simulate above cases, modelling was used the transient analysis program PSCAD/EMTDC. By using this, the customer installed emergency generator and the grid was implemented. We compared three cases of asynchronous transition based on the basic case and proposed improvement by controlling the governor of emergency generator.

• Bulletin of the Korean Chemical Society
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• v.34 no.7
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• pp.1961-1966
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• 2013

Theoretical investigations have been performed for the ground state ($S_0$) and the first excited state ($S_1$) of the hydrogen bonded green fluorescent protein (GFP) model. The potential energy surface (PESs) of $S_0$ was obtained by B3LYP method and that of $S_1$ was obtained by CIS method. Based on the relative stabilities of species and the energy barriers for the proton transfer, it was found that proton transfer could take place both under the ground state and the first excited state. As determined by the proton motions along the reaction coordinate, both the ground state proton transfer (GSPT) and the excited state proton transfer (ESPT) are considered as a concerted and asynchronous process.

• Journal of Korea Game Society
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• v.14 no.6
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• pp.59-68
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• 2014

Memory bandwidth requirements of UHD (Ultra High Definition $4096{\times}2160$) game scenes have been much more increasing. This paper presents a lossless DPCM-GR based compression algorithm using CUDA for solving the memory bandwidth problem without sacrificing image quality, which is modified from DDPCM-GR [4] to support bit parallel pipelining. The memory bandwidth efficiency increases because of using the shared memory of CUDA. Various asynchronous transfer configurations which can overlap the kernel execution and data transfer between host and CUDA are implemented with the page-locked host memory. Experimental results show that the maximum 31.3 speedup is obtained according to CPU time. The maximum 30.3% decreases in the computation time among various configurations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.12
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• pp.2635-2642
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• 2012

MOST(Media Oriented Systems Transport) is a network protocol for vehicle multimedia, where it guarantees large bandwidth and reliability. However, previous MOST device utilized I2C or I2S communication method to data manage or transfer, Bandwidth of MOST have increased and additional equipments are added to one device, requiring a larger form of bandwidth communication method. Therefore, this research suggests of the methods in improving the efficiency of asynchronous data transfer, and suggest an algorithm, which will improve the reliability.

• The Magazine of the IEIE
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• v.18 no.12
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• pp.29-38
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• 1991

CCITT에 의해서 표준화 되고 있는 SDH(synchronous digital hierarchy)기본의 광대역 전송방식과 이의 향후 응용 방향에 대해 개관한다. 또한 광대역 전송방식으로서 고려될 수 있는 STM(synchronous transfer mode)망과 ATM(asynchronous transfer mod)망의 구조를 살펴보고 1991년도를 중심으로 일어나고 있는 이들 각각의 국내ㆍ외적인 표준화 동향, 기술개발 현황, 그리고 망구축 동향 등에 대해서 간단히 기술한다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.349-352
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• 2001

As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.521-530
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• 1989

Broadband ATM(Asynchronous Transfer Mode) networking techniques based on lightwave technology and high speed integrated circuits appear to be the choice of transport technology for broadband ISDN. Among other problems, the issue of video transport over broadband packet(ATM) networks still requries further investigation. In this paper, the problems of transporting video signals over a broaband packet network are investigated together with possible solutions. In particular, clock recovery packet loss compensation and transport technique based on hierarchical video coding scheme are described in detail. This would allow efficient bandwidth sharing and minimum degradation in video quality.