• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.05a
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• pp.88-90
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• 2012

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) with a rail-to-rail input range. The proposed SAR ADC consists of a capacitor digital-analog converter (DAC), a SAR logic and a comparator. To reduce the frequency of an external clock, the internal clock which is asynchronously generated by the SAR logic and the comparator is used. The time-domain comparator with a offset calibration technique is used to achieve a high resolution. To reduce the power consumption and area, a split capacitor-based differential DAC is used. The designed asynchronous SAR ADC is fabricated by using a 0.18 um CMOS process, and the active area is $420{\times}140{\mu}m^2$. It consumes the power of 0.818 mW with a 1.8 V supply and the FoM is 91.8 fJ/conversion-step.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.49-58
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• 2016

In designing heterogeneous architecture based application-specific network-on-chips (NoCs), the opportunities of performance improvement would be expanded when applying asynchronous on-chip communication protocol. This is because the wire latency can be configured independently considering the wirelength of each link. In this paper, we develop the delay model of link-wire-length in asynchronous NoC and propose simulated annealing (SA) based floorplan-aware topology generation algorithm to optimize link-wirelengths. Incorporating the generated topology and the associated latency values across all links, we evaluate the performance using the floorplan-annotated sdf (standard delay format) file and RTL-synthesized gate-level netlist. Compared to TopGen, one of general topology generation algorithms, the experimental results show the reduction in latency by 13.7% and in execution time by 11.8% in average with regards to four applications.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1542-1547
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• 2012

Asynchronous phenomenon occurs on the synchronous generators under power system when a generator's amplitude of electromagnetic force, phase angle, frequency and waveform etc become different from those of other synchronous generators which can follow instantly varying speed of turbine. Because the amplitude of electromagnetic force, phase frequency and waveform differ from those of other generators with which are to be put into parallel operation due to the change of excitation condition for load sharing and the sharing load change, if reactive current in the internal circuit circulates among generators, the efficiency varies and the stator winding of generators are overheated by resistance loss. When calculation method of protection settings and logic for protection of generator asynchronization will be recommended, a distance relay scheme is commonly used for backup protection. This scheme, called a step distance protection, is comprised of 3 steps for graded zones having different operating time. As for the conventional step distance protection scheme, zone 2 can exceed the ordinary coverage excessively in case of a transformer protection relay especially. In this case, there can be overlapped protection area from a backup protection relay and, therefore, malfunctions can occur when any fault occurs in the overlapped protection area. Distance relays and overcurrent relays are used for backup protection generally, and both relays have normally this problem, the maloperation, caused by a fault in the overlapped protection area. Corresponding to an IEEE standard, this problem can be solved with the modification of the operating time. On the other hand, in Korea, zones are modified to cope with this problem in some specific conditions. These two methods may not be obvious to handle this problem correctly because these methods, modifying the common rules, can cause another coordination problem. To overcome asynchronizing protection, this paper describes an improved backup protection coordination scheme using a new logic that will be suggested.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.414-422
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• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.53-59
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• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• The Transactions of the Korea Information Processing Society
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• v.4 no.12
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• pp.2985-2995
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• 1997

In this paper, we proposed the "synchronous & asynchronous distance education system" which is able to interact among teachers and students for open education in cyberspace, and it is based telecommunication technology and multimedia technology. Specially, This system gets rid of the nufamiliarity and inconvenient feeling during the distance education. Also it supports the mediation of floor mode, for a group lecture and supports the synchronous mode for face-to-face effective and asynchronous mode for self-learning. The asynchronous mode has the down load function and the consultant mode (between teacher and student). The element technologies of this system consists of application sharing technique, whiteboard, various video window display, audio support, user interface, environment setup, session management, access control, network control and media control for collaborative distance education.

• Journal of Advanced Marine Engineering and Technology
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• v.36 no.6
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• pp.837-843
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• 2012

Asynchronous motors are widely used in many fields. The various starting methods have been developed for the asynchronous motors which have large power compared to source power. The most popular ways to start the motors are to reduce the voltage of motor's stator or change the resistance fed rotor. It is needed to the specific time to reduce the voltage and change the resistance at a specific step. We call it the switching time. It is very difficult to know the switching time exactly. It varies with different types of motors as well as load characteristics. Thus, this paper focuses on the design and development for the mathematical models of motor and load. And then it is implemented in SIMULINK in order to calculate this time. The simulation results are both compared and discussed in detail so that it can be applied for new system with various motors and loads.

• Journal of Arbitration Studies
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• v.19 no.2
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• pp.155-178
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• 2009

The ODR can be categorized into four distinctive types. First type is the asynchronous non-demeanour method. Second type is the asynchronous demeanour method. Third type is the synchronous demeanour method. Fourth type is the synchronous demeanour method. A typical example of the asynchronous and non-demeanour method is e-mail. The example of the synchronous and non-demeanour method is tele conference. The example of the asynchronous demeanour method is video recordings. The example of synchronous and demeanour method is video conference. The primary benefit of e-mail is to avoid the physical violence. But the costs of email is the lack of emotional aspects of disputants. The benefits of tele conference is ease of use, and reduces the negative aspects of face to face communication. but the costs are limitation of the exchange of written information. The benefits of video conference is the approximation of face to face communication by providing oral as well as visual communication. but it is insufficient to represent eye contact. The common limitations of ODR are as follows. First is the lack of human face. Second is the neutrality of arbitrators and mediators. Third is the authenticity of electronic document. Fourth is the digital divide across South and North and generations. Fifth is the cross-cultural communication. The development strategy of ODR is the training and education of arbitrators and mediators in the area of writing skill. Furthermore, it is necessary to supplement the weakness of email via diverse kinds of expressions to show emotions. Finally, it is necessary to train neutrals in the area of cross-cultural communication.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.19-25
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• 2004

In this paper, we propose optimal and suboptimal serial code acquisition schemes for chip-asynchronous direct-sequence spread-spectrum systems. The conventional serial code acquisition scheme is to compare each value of correlator outputs with a threshold individually. However, such a scheme is optimum only under the chip-synchronous assumption which is actually very difficult to be held prior to acquisition at the receiver because the signal-to-noise ratios before despreading are very low. In this paper, an optimal serial code acquisition scheme is derived based on the maximum-likelihood criterion under the more realistic and general chip-asynchronous environments. A suboptimal scheme, which is simpler but yields comparable performance to the optimal one, is also derived based on the criterion of local detection power Numerical results show that, under the chip-asynchronous environments, both the optimal and suboptimal serial code acquisition schemes outperform the conventional serial code acquisition scheme.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1915-1922
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• 2012

In this paper, the Solar Inverter will be monitored by using the AJAX(Asynchronous JavaScript and XML). AJAX is the one of the technologies that can make the RIA(Rich Internet Application) with DHTML(Dynamic Hyper Text Makeup Language) and other java script technology. By using this, a strong application program that is comparable to the general application program can be made. With an existing data-processing technique, the request and response of data can't be processed dynamically on the same page. However, real-time monitoring of data and operation statuses can be confirmed by using the AJAX an asynchronous method of communication. Also without changing the page, the amount of data transmission used the AJAX with significantly small amounts of data to build a Solar Inverter monitoring system that is able to efficiently handle management and monitoring, operating all functions within one page.