• Title/Summary/Keyword: Arsenic implantation

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A Study of Dopant Distribution in SiGe Using Ion Implantation and Thermal Annealing (SiGe에 이온 주입과 열처리에 의한 불순물 분포의 연구)

  • Jung, Won-Chae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.31 no.6
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    • pp.377-385
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    • 2018
  • For the investigation of dopant profiles in implanted $Si_{1-x}Ge_x$, the implanted B and As profiles are measured using SIMS (secondary ion mass spectrometry). The fundamental ion-solid interactions of implantation in $Si_{1-x}Ge_x$ are discussed and explained using SRIM, UT-marlowe, and T-dyn programs. The annealed simulation profiles are also analyzed and compared with experimental data. In comparison with the SIMS data, the boron simulation results show 8% deviations of $R_p$ and 1.8% deviations of ${\Delta}R_p$ owing to relatively small lattice strain and relaxation on the sample surface. In comparison with the SIMS data, the simulation results show 4.7% deviations of $R_p$ and 8.1% deviations of ${\Delta}R_p$ in the arsenic implanted $Si_{0.2}Ge_{0.8}$ layer and 8.5% deviations of $R_p$ and 38% deviations of ${\Delta}R_p$ in the $Si_{0.5}Ge_{0.5}$ layer. An analytical method for obtaining the dopant profile is proposed and also compared with experimental and simulation data herein. For the high-speed CMOSFET (complementary metal oxide semiconductor field effect transistor) and HBT (heterojunction bipolar transistor), the study of dopant profiles in the $Si_{1-x}Ge_x$ layer becomes more important for accurate device scaling and fabrication technologies.

Study on Structural properties of As Ion -Implanted Si (As이온이 주입된 Si의 구조적 특성 연구)

  • 믄영희;배인호;김말문;한병국;김창수;홍승수;신용현;정광화
    • Journal of the Korean Vacuum Society
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    • v.5 no.3
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    • pp.218-222
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    • 1996
  • STrained layers and strain depth profile of high dose As ion implanted (100) si wafer annealed at various temperatures have been investigated by means of X-ray double crystal diffractometry (X-ray DCD). The results obtained by x-ray rocking curve analysis showed a defect layer at the original amorphous /crystalline interface of 1400$\AA$ depth. In addition arsenic ion concentrtion profiles and defect distributions in depth were obtained by the SIMS and TRIM -code simulation . the positive strain depth profile determined from the rocking curve analysis were only presented under 0.14 $\mu$m from the surface for samples ananelaed at $600^{\circ}C$. The results was shown that the thickness of amprphous layer is 0.14 $\mu$m indirectry, and it was good agreement with the TRIM -Code simulation. Additionally, it could be thought that the positive strain have been affected residual intersitial atoms under the amorphous/crystalline interface formed by ion implantation.

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Ultra Shallow Junction wish Source/Drain Fabricated by Excimer Laser Annealing and realized sub-50nm n-MOSFET (엑시머 레이져를 이용한 극히 얕은 접합과 소스, 드레인의 형성과 50nm 이하의 극미세 n-MOSFET의 제작)

  • 정은식;배지철;이용재
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.562-565
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    • 2001
  • In this paper, novel device structures in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA). Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20nm for arsenic dosage(2${\times}$10$\_$14//$\textrm{cm}^2$), exciter laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm and realized sub-50nm n-MOSFET.

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Characterization of Two-Dimensional Impurity Profile in Silicon (실리콘에서의 2차원적 불순물 분포의 산출)

  • Yang, Yeong Yil;Kyung, Chong Min
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.23 no.6
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    • pp.929-935
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    • 1986
  • In this paper, we describe the physical modelling and numerical aspects of a program called PRECISE(Program for Efficient Calculation of Impurity Profile in Semiconductor by Elimination) which calcualtes a two-dimensional impurity profile in silicon due to diffusion and ion implantation steps. The PRECISE enables rapid prediction of the two-dimensional impurity profile near the mask edge-or the bird's beak during the local oxidation process. This has been developed by modifying the existing one-dimentional simulator, DIFSIM(DIFfusion SIMulator to include models for arsenic diffusion and emitter dip effect which were found out to agree fairly well with the xperimental data.

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Dual-Gate Surface Channel 0.1${\mu}{\textrm}{m}$ CMOSFETs

  • Kwon, Hyouk-Man;Lee, Yeong-Taek;Lee, Jong-Duk;Park, Byung-Gook
    • Journal of Electrical Engineering and information Science
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    • v.3 no.2
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    • pp.261-266
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    • 1998
  • This paper describes the fabrication and characterization of dual-polysilicon gated surface channel 0.1$\mu\textrm{m}$ CMOSFETs using BF2 and arsenic as channel dopants. We have used and LDD structure and 40${\AA}$ gate oxide as an insulator. To suppress short channel effects down to 0.1$\mu\textrm{m}$ channel length, shallow source/drain extensions implemented by low energy implantation and SSR(Super Steep Retrograde) channel structure were used. The threshold voltages of fabricated CMOSFETs are 0.6V. The maximum transconductance of nMOSFET is 315${\mu}$S/$\mu\textrm{m}$, and that of pMOSFET is 156 ${\mu}$S/$\mu\textrm{m}$. The drain saturation current of 418 ${\mu}$A/$\mu\textrm{m}$, 187${\mu}$A/$\mu\textrm{m}$ are obtained. Subthreshold swing is 85mV/dec and 88mV/dec, respectively. DIBL(Drain Induced Barrier Lowering) is below 100mV. In the device with 2000${\AA}$ thick gate polysilicon, depletion in polysilicon near the gate oxide results in an increase of equivalent gate oxide thickness and degradation of device characteristics. The gate delay time is measured to be 336psec at operation voltage of 2V.

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Three-dimensional Modeling of Transient Enhanced Diffusion (과도 증속 확산(TED)의 3차원 모델링)

  • 이제희;원태영
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.35D no.6
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    • pp.37-45
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    • 1998
  • In this paper, we report the first three-dimensional simulation result of the transient enhanced diffusion(TED) of dopants in the ion-implanted silicon by employing our 3D semiconductor process simulator, INPROS system. In order to simulate three-dimensional TED redistribution of dopants in silicon, the dopant distributions after the ion implantation was calculated by Monte Carlo(MC) method, followed by finite element(FE) numerical solver for thermal annealing. Excellent agreement between the simulated 3D profile and the SIMS data has been obtained for ion-implanted arsenic and phosphorus after annealing the boron marker layer at 75$0^{\circ}C$ for 2 hours. Our three-dimensional TED simulation could successfully explain the reverse short channel effect(RSCE) by taking the 3D point defect distribution into account. A coupled TED simulation and device simulation allows reverse short channel effect on threshold to be accurately predicted.

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Ultra shallow function Formation of Low Sheet Resistance Using by Laser Annealing (레이져 어닐링을 이용한 낮은 면저항의 극히 얕은 접합 형성)

  • 정은식;배지철;이용재
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2001.05a
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    • pp.349-352
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    • 2001
  • In this paper, novel device structure in order to realize ultra fast and ultra small silicon devices are investigated using ultra-high vacuum chemical vapor deposition(UHVCVD) and Excimer Laser Annealing (ELA) for ultra pn junction formation. Based on these fundamental technologies for the deep sub-micron device, high speed and low power devices can be fabricated. These junction formation technologies based on damage-free process for replacing of low energy ion implantation involve solid phase diffusion and vapor phase diffusion. As a result, ultra shallow junction depths by ELA are analyzed to 10~20 nm for arsenic dosage (2$\times$10$^{14}$ $\textrm{cm}^2$), excimer laser source(λ=248nm) is KrF, and sheet resistances are measured to 1k$\Omega$/$\square$ at junction depth of 15nm.

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Review of Hazardous Agent Level in Wafer Fabrication Operation Focusing on Exposure to Chemicals and Radiation (반도체 산업의 웨이퍼 가공 공정 유해인자 고찰과 활용 - 화학물질과 방사선 노출을 중심으로 -)

  • Park, Donguk
    • Journal of Korean Society of Occupational and Environmental Hygiene
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    • v.26 no.1
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    • pp.1-10
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    • 2016
  • Objectives: The aim of this study is to review the results of exposure to chemicals and to extremely low frequency(ELF) magnetic fields generated in wafer fabrication operations in the semiconductor industry. Methods: Exposure assessment studies of silicon wafer fab operations in the semiconductor industry were collected through an extensive literature review of articles reported until the end of 2015. The key words used in the literature search were "semiconductor industry", "wafer fab", "silicon wafer", and "clean room," both singly and in combination. Literature reporting on airborne chemicals and extremely low frequency(ELF) magnetic fields were collected and reviewed. Results and Conclusions: Major airborne hazardous agents assessed were several organic solvents and ethylene glycol ethers from Photolithography, arsenic from ion implantation and extremely low frequency magnetic fields from the overall fabrication processes. Most exposures to chemicals reported were found to be far below permissible exposure limits(PEL) (10% < PEL). Most of these results were from operators who handled processes in a well-controlled environment. In conclusion, we found a lack of results on exposure to hazardous agents, including chemicals and radiation, which are insufficient for use in the estimation of past exposure. The results we reviewed should be applied with great caution to associate chronic health effects.

Temperature Dependence of Resistivity in As Implanted LPCVD Polycrystalline Silicon Films (LPCVD로 제조된 다결정실리콘에 As를 주입한 시료의 비저항에 대한 온도의존성 연구)

  • Ha, Hyoung-Chan;Kim, Chung-Tae;Ko, Chul-Gi;Chun, Hui-Gon;Oh, Kye-Hwan
    • Korean Journal of Materials Research
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    • v.1 no.1
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    • pp.23-28
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    • 1991
  • The resistivity of polycrystalline silicon film deposited by low pressure chemical vapor deposition and doped by arsenic Implantation has been investigated as a function of dopant concentration and testing temperature ranging from $25^{\circ}C$ to $105^{\circ}C$ . The resistivity vs. doping concentration curve had a peak point with highest activation energy with respect to the dependence of the resistivity on temperature. We showed that $O_2$ plasma anneal followed by heat-treatment in $N_2$ ambient was able to recover the resistivity degraded by the plasma deposited passivation layers.

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A Study of $Sb_2O_3$ Beam Tuning for SSR Channel on Bi-CMOS Process (Bi-CMOS공정중 SSR 채널 형성을 위한 $Sb_2O_3$ 빔튜닝 방법 연구)

  • Choi, Min-Ho;Kim, Nam-Hoon;Kim, Sang-Yong;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.07a
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    • pp.369-372
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    • 2004
  • The characteristics of antimony implants are relatively well-known. Antimony has lower diffusion coefficient, shorter implantation range, and smaller scattering as compared with conventional dopants such as phosphorous and arsenic. It has been commonly used in the doping of buried layer in Bi-CMOS process. In this paper, characteristics and appropriate condition of monitoring in antimony implant beam tuning using $Sb_2O_3$ were investigated to get a reliable process. TW(Thema Wave) and Rs(Sheet Resistance) test were carried out to set up condition of monitoring for stable operation through the periodic inspection of instruction condition. The monitoring was progressed at the point that the slant of Rs varied significantly to investigate the variation of instruction accurately.

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