• Title/Summary/Keyword: Array test

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Effects of Underfills on the Dynamic Bending Reliability of Ball Grid Array Board Assembly (Ball Grid Array 보드 어셈블리의 동적굽힘 신뢰성에 미치는 언더필의 영향)

  • Jang, Jae-Won;Bang, Jung-Hwan;Yoo, Se-Hoon;Kim, Mok-Soon;Kim, Jun-Ki
    • Korean Journal of Materials Research
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    • v.21 no.12
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    • pp.650-654
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    • 2011
  • In this paper, the effects of conventional and newly developed elastomer modified underfill materials on the mechanical shock reliability of BGA board assembly were studied for application in mobile electronics. The mechanical shock reliability was evaluated through a three point dynamic bending test proposed by Motorola. The thermal properties of the underfills were measured by a DSC machine. Through the DSC results, the curing condition of the underfills was selected. Two types of underfills showed similar curing behavior. During the dynamic bending reliability test, the strain of the PCB was step increased from 0.2% to 1.5% until the failure circuit was detected at a 50 kHz sampling rate. The dynamic bending reliability of BGA board assembly using elastomer modified underfill was found to be superior to that of conventional underfill. From mechanical and microstructure analyses, the disturbance of crack propagation by the presence of submicron elastomer particles was considered to be mainly responsible for that result rather than the shear strength or elastic modulus of underfill joint.

A Study of Testing Method for Diagnostic Ultrasonic Array Probe through Pattern Analysis of Acoustic-Fields with Probe Channel Division (채널별 음장분포 분석을 통한 진단용 초음파 어레이 프로브의 평가방법에 관한 연구)

  • Yoo, B.C.;Choi, H.H.;Noh, S.C.;Min, H.K.;Kwon, J.W.
    • Journal of Biomedical Engineering Research
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    • v.27 no.5
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    • pp.229-236
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    • 2006
  • The acoustic field analysis method is the superior calibration method for rectifying the ultrasonic probe sensitivity. This method also can be applied to evaluate the probe performance in clinical fields without numerical analysis and precise measurements. In this paper, we propose the method of acoustic field pattern analysis with probe channel division for the evaluation of diagnostic ultrasound probe characterization. In order to verify our purpose, we performed a set of experiments. We measured the acoustic-field pattern of the three inferiority probes by channel division to evaluate an acoustic field distribution and impulse response characteristics. By comparing the results of acoustic field measurement method with that of conventional method such as impulse response and live image test for linear array probes, it is demonstrated that the ultrasound field measurement method is more effective then conventional method in detection of defective elements.

3D Measurement System of Wire for Automatic Pull Test of Wire Bonding (Wire bonding 자동 전단력 검사를 위한 wire의 3차원 위치 측정 시스템 개발)

  • Ko, Kuk Won;Kim, Dong Hyun;Lee, Jiyeon;Lee, Sangjoon
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.12
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    • pp.1130-1135
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    • 2015
  • The bond pull test is the most widely used technique for the evaluation and control of wire bond quality. The wire being tested is pulled upward until the wire or bond to the die or substrate breaks. The inspector test strength of wire by manually and it takes around 3 minutes to perform the test. In this paper, we develop a 3D vision system to measure 3D position of wire. It gives 3D position data of wire to move a hook into wires. The 3D measurement method to use here is a confocal imaging system. The conventional confocal imaging system is a spot scanning method which has a high resolution and good illumination efficiency. However, a conventional confocal systems has a disadvantage to perform XY axis scanning in order to achieve 3D data in given FOV (Field of View) through spot scanning. We propose a method to improve a parallel mode confocal system using a micro-lens and pin-hole array to remove XY scan. 2D imaging system can detect 2D location of wire and it can reduce time to measure 3D position of wire. In the experimental results, the proposed system can measure 3D position of wire with reasonable accuracy.

Filed Programmable Logic Control and Test Pattern Generation for IoT Multiple Object switch Control (사물인터넷 환경에서 다중 객체 스위치 제어를 위한 프로그래밍 가능한 로직제어 및 테스트 패턴 형성)

  • Kim, Eung-Ju;Jung, Ji-Hak
    • Journal of Internet of Things and Convergence
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    • v.6 no.1
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    • pp.97-102
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    • 2020
  • Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

COMS Shock Test Assessment by Using the Extrapolation Method (외삽법을 이용한 천리안위성 충격시험 분석)

  • Lee, Ho-Hyung
    • Journal of the Korean Society for Aeronautical & Space Sciences
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    • v.40 no.5
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    • pp.439-445
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    • 2012
  • The COMS(Communication, Ocean, and Meteorological Satellite) is subjected to shock loads when the stage or fairing of a launch vehicle is separated and the satellite is separated from the launch vehicle during the launch vehicle flight. And, after the satellite is separated from the launcher, the COMS is subjected to shock loads when the solar array is deployed, Ka-Band communication antenna is deployed, and meteorological imager radiator cover is released. In order to validate the satellite safety against these shock loads on ground, shock tests were performed. In this paper, the shock tests performed in the course of the COMS development are described, and the method to assess the test result is presented with an example of Geostationary Ocean Color Imager(GOCI). In Ariane-5 launch vehicle, the clampband release shock for satellite separation is lower than the fairing or stage separation. In this paper, the extrapolation method to take into account the maximum shock load from the launch vehicle by using the satellite separation shock test result is also introduced.

Acoustic test of the payload fairing of Korea satellite launch vehicle (소형 위성 발사체의 페이로드 페어링부에 대한 음향 가진 시험)

  • Park, S.H.;Seo, S.H.
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2007.05a
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    • pp.220-223
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    • 2007
  • Acoustic test of the payload fairing of Korea satellite launch vehicle was conducted to verify the performance of acoustic protection system installed inside the payload fairing. This paper briefly introduces the acoustic test procedures and its results. Overall 148 dB acoustic loads were exerted on the payload fairing structures which mated with the upper stage structure of the launch vehicle. In order to verify the increase of insertion loss by the acoustic protection system, two kinds of test were performed. One is conducted with acoustic protection system and the other without acoustic protection system. Internal acoustic loads as well as external ones were measured and the measured insertion losses were compared with the requirement. The results showed that the acoustic protection system increases the insertion loss by more than 6 dB above 125 Hz. They also indicated that some design modification of Helmholtz resonator array is required to increase the insertion loss at a cavity resonant frequency.

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A Study on the Minimal Test Pattern of the RAM (RAM의 최소 테스트 패턴에 관한 연구)

  • 김철운;정우성;김태성
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.11a
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    • pp.23-25
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    • 1996
  • In this paper aims at studying the minimal test pattem of the RAM. This also propose a scheme of testing faults from the new fault model using the LLB. The length of test patterns are 6N(1-wsf), 9.5N(2-wsf), 7N(3-wsfl, 3N(4-wsf) operations in N-bit RAM. This test techniques can write into memory cell the number of write operations is reduced and then much testing time is saved. A test set which detects all positive-negative static t-ws faults for t=0, 1, 2, 3, 4 and detects all pattern sensitive fault in memory array. A new fault model, which encompasses the existing fault model Is proposed.

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Development of a General Purpose PID Motion Controller Using a Field Programmable Gate Array

  • Kim, Sung-Su;Jung, Seul
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.360-365
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    • 2003
  • In this paper, we have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers on a single chip are implemented as a system-on-chip for multi-axis motion control. We also develop a PC GUI for an efficient interface control. Comparing with the commercial motion controller LM 629 it has multi-independent PID controllers so that it has several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, robot finger is controlled. The robot finger has three fingers with 2 joints each. Finger movements show that position tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

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Wafer level vertical interconnection method for microcolumn array (마이크로컬럼 어레이에 적용 가능한 웨이퍼단위의 수직 배선 방법)

  • Han, Chang-Ho;Kim, Hyeon-Cheol;Kang, Moon-Koo;Chun, Kuk-Jin
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.793-796
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    • 2005
  • In this paper, we propose a method which can improve uniformity of a miniaturized electron beam array for inspection of very small pattern with high speed using vertical interconnection. This method enables the individual control of columns so that it can reduce the deviation of beam current, beam size, scan range and so on. The test device that used vertical interconnection method was fabricated by multiple wafer bonding and metal reflow. Two silicon and one glass wafers were bonded and metal interconnection by melting of electroplated AuSn was performed. The contact resistance was under $10{\Omega}$.

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A CMOS integrated circuit design of charge-sharing scheme for a capacitive fingerprint sensor (용량형 지문인식센서를 위한 전하분할 방식 감지회로의 CMOS 구현)

  • Nam, Jin-Moon;Lee, Moon-Key
    • Journal of Sensor Science and Technology
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    • v.14 no.1
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    • pp.28-32
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    • 2005
  • In this paper, a CMOS integrated detection circuit for capacitive type fingerprint sensor signal processing is described. We designed a detection circuit of charge-sharing sensing scheme. The proposed detection circuit increases the voltage difference between a ridge and valley. The test chip is composed of $160{\times}192$ array sensing cells (12 by $12.7{\;}mm^{2}$). The chip was fabricated on a 0.35 m standard CMOS process. Measured difference voltage between a ridge and valley was 0.95 V.