• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.10 no.3
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• pp.237-242
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• 2016

The major advantage of slip-ring technology in Spiral CT is that it facilitates continuous rotation of the x-ray tube, so that volume data can be acquired from a patient quickly. Not only for such a fast scan, but also for the dose reduction purpose, high signal-to-noise ratio and fast data acquisition system is required. In this study, we have built a multi-channel photodetector and multi-channel data acquisition system for CT application. The detector module consisted of CdWO4 crystal and Si photodiode in 16 channels. For the performance test of the preamplifier stage, both the transimpedance and switched integrator types are optimized for the photodetector modules. Switched integrator showed better noise performance in the limited bandwidth which is suitable for the current CT application. The control sequence for data acquisition and 20 bit ADC is designed with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and implemented on FPGA(Field Programmable Gate Array) chip. Our Si photodiode detector module coupled to CdWO4 crystal showed comparable signal with other commercially available photodiode for CT. Switched integrator type showed higher SNR but narrower bandwidth compared to transimpedance preamplifier. Digital hardware is designed by FPGA, so that the control signal could be redesigned without hardware alteration.

• Korean Journal of Acupuncture
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• v.23 no.3
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• pp.133-160
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• 2006

Objectives : Scolopendrae Corpus has a broad array of clinical applications in Korean medicine, including treatment of inflammatory conditions such as arthritis. To explore the global gene expression profiles in human Raw cell lines treated with Scolopendrae Corpus herbal-acupuncture solution (SCHAS), cDNA microarray analysis was performed. Methods : The Raw 264.7 cells were treated with lipopolysaccharide (LPS), SCHAS, or both. The primary data was normalized by the total spots of intensity between two groups, and then normalized by the intensity ratio of reference genes such as housekeeping genes in both groups. The expression ratio was converted to log2 ratio. Normalized spot intensities were calculated into gene expression ratios between the control and treatment groups. Greater than 2 fold changes between two groups were considered to be of significance. Results : Of the 8 K genes profiled in this study, with a cut-off level of two-fold change in the expression, 20 genes (BCL2-related protein A1, MARCKS-like 1, etc.) were upregulated and 5 genes (activated RNA polymerase II transcription cofactor 4, calcium binding atopy-related autoantigen 1, etc.) downregulated following LPS treatment. 139 genes (kell blood group precursor (McLeod phenotype), ribosomal protein S7, etc.) were upregulated and 42 genes (anterior gradient 2 homolog (xenopus laevis), phosphodiesterase 8B, etc.) were downregulated following SCHAS treatment. And 10 genes (yeast saccharomyces cerevisiae intergeneic sequence 4-1, mitogen-activated protein kinase 1, etc.) were upregulated and 8 genes (spermatid perinuclear RNA binding protein, nuclear receptor binding protein 2, etc.) were downregulated following co-stimulation of SCHAS and LPS. Discussions : It is thought that microarrays will play an ever-growing role in the advance of our understanding of the pharmacological actions of SCHAS in the treatment of arthritis. But further studies are required to concretely prove the effectiveness of SCHAS.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Nutrition Research and Practice
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• v.2 no.4
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• pp.289-294
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• 2008

Pre-B-cell leukemia transcription factor 1 (PBX1), which is located on chromosome 1q23, was recently reported to be associated with type 2 diabetes mellitus. We examined whether single nucleotide polymorphisms (SNPs) of the PBX1 gene are associated with overweight/obesity in a Korean population. We genotyped 66 SNPs in the PBX1 gene and investigated their association with clinical phenotypes found in 214 overweight/obese subjects and 160 control subjects using the Affymetrix Targeted Genotyping chip array. Seven SNPs (g.+75l86C>T, g.+78350C>A, g.+80646C>T, g.+138004C>T, g.+185219G>A, g.+191272A>C, and g.+265317T>A) were associated with the risk of obesity in three models (codominant, dominant, and recessive) (P=0.007-0.05). Haplotype 1 (CAC) and 3 (TAC) of block 3 and haplotype 2 (GGAAT) of block 10 were also strongly associated with the risk of obesity. In the control group, subjects that had homozygote for the major allele for both g.+185219G>A and g.+191272A>C showed lower high density lipoprotein-cholesterol (HDL-C) level compared to those possessing the minor allele, suggesting that the association between the homozygote for the major allele for both g.+185219G>A and g.+191272A>C and HDL-C is attributable to the increased risk of obesity. This study suggests that the PBX1 gene is a possible risk factor in overweight/obese patients.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2366-2373
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• 2007

In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

• Genes and Genomics
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• v.40 no.12
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• pp.1373-1382
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• 2018

Hanwoo and Chikso are classified as Korean native cattle breeds that are currently registered with the Food and Agriculture Organization. However, there is still a lack of genomic studies to compare Hanwoo to Chikso populations. The objective of this study was to perform genome-wide analysis of Hanwoo and Chikso populations, investigating the genetic relationships between these two populations. We genotyped a total of 319 cattle including 214 Hanwoo and 105 Chikso sampled from Gangwon Province Livestock Technology Research Institute, using the Illumina Bovine SNP50K Beadchip. After performing quality control on the initially generated datasets, we assessed linkage disequilibrium patterns for all the possible SNP pairs within 1 Mb apart. Overall, average $r^2$ values in Hanwoo (0.048) were lower than Chikso (0.074) population. The genetic relationship between the populations was further assured by the principal component analysis, exhibiting clear clusters in each of the Hanwoo and Chikso populations, respectively. Overall heterozygosity for Hanwoo (0.359) was slightly higher than Chikso (0.345) and inbreeding coefficient was also a bit higher in Hanwoo (-0.015) than Chikso (-0.035). The average $F_{ST}$ value was 0.036 between Hanwoo and Chikso, indicating little genetic differentiation between those two breeds. Furthermore, we found potential selection signatures including LRP1B and NTRK2 genes that might be implicated with meat and reproductive traits in cattle. In this study, the results showed that both Hanwoo and Chikso populations were not under severe level of inbreeding. Although the principal component analysis exhibited clear clusters in each of the populations, we did not see any clear evidence that those two populations are highly differentiated each other.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.12C
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• pp.1288-1298
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• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.