• Title/Summary/Keyword: Array Testing

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Triploidy that escaped diagnosis using chromosomal microarray testing in early pregnancy loss: Two cases and a literature review

  • Park, Ji Eun;Park, Ji Kwon;Kang, Min Young;Jo, Hyen Chul;Cho, In Ae;Baek, Jong Chul
    • Journal of Genetic Medicine
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    • v.16 no.2
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    • pp.76-80
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    • 2019
  • About 15% to 20% of all clinically recognized pregnancies result in spontaneous abortion or miscarriage, and chromosomal anomalies can be identified in up to 50% of first trimester miscarriages. Chromosomal microarray analysis (CMA) is currently considered first-tier testing for detecting fetal chromosomal abnormalities and is supported by the absence of cell culture failure or erroneous results due to cell contamination in pregnancy loss. Triploidy is a lethal chromosome number abnormality characterized by an extra haploid set of chromosomes. Triploidy is one of the most common chromosomal aberrations in first trimester spontaneous abortions. Here, we report two cases of triploidy abortion that were not detected using array comparative genomic hybridization-based CMA. The aim of this report was to remind clinicians of the limitations of chromosomal testing and the misdiagnosis that can result from biased test selection.

Design, Implementation and Testing of HF transformers for Satellite EPS Applications

  • Zahran, Mohamed
    • Journal of Power Electronics
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    • v.8 no.3
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    • pp.217-227
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    • 2008
  • The electric power subsystems (EPS) of most remote sensing satellites consist of a solar array as a source of energy, a storage battery, a power management and control (PMC) unit and a charge equalization unit (CEU) for the storage battery. The PMC and CEU use high frequency transformers in their power modules. This paper presents a design, implementation and testing results of a high frequency transformer for the EPS of satellite applications. Two approaches are used in the design process of the transformer based on the pre-determined transformer specifications. The transformer is designed based on an ETD 29 ferrite core. The implemented transformer consists of one center-tapped primary coil with eleven center-tapped secondary coils. The offline calculation results and measured values of R, L for transformer coils are convergence. A test circuit for measuring the transformer parameters like voltage, current and B-H hysteresis was implemented and applied. The test results confirm that the voltage waveforms of both primary and secondary coils were as desired. No overlapping occurred between the control signal and the transformer, which was not saturated during testing even during a short circuit test of the secondary channels. The dynamic B-H loop characteristics of the used transformer cores were measured. The sample test results are given in this paper.

Optimization for Component Noise Validation Test by Evaluation of Noise Control Factors for Suspension (현가장치 소음 발생인자 평가를 통한 부품소음 검증시험 최적화)

  • Son, Myungkoon;Lee, Taeyong;Lee, Sangbok;Lee, Seul
    • Transactions of the Korean Society of Automotive Engineers
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    • v.25 no.3
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    • pp.344-349
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    • 2017
  • Suspension noise from under a passenger car is one of the important factors that impact the perceptual quality for drivers. However, it is difficult to validate this by component level testing in the early stage of development, because suspension noise caused by interaction of the related parts has been found at saleable vehicles late during development or at the manufacturing stage, when many customers have already filed for claims. This study proposed a validation testing under research by the DFSS process that enables reproduction of vehicle level noise by component level testing using a shock absorber with the related parts, such as urethane bumper and top mount. This study also developed a compromised test matrix while analyzing the noise factors through experimental design and analysis of variance to determine what factors can affect noise. Based on this study, we expect that the vehicle level and customer claim can be validated during initial development timing by a more reliable component noise validation test.

Development of a truncation artifact reduction method in stationary inverse-geometry X-ray laminography for non-destructive testing

  • Kim, Burnyoung;Yim, Dobin;Lee, Seungwan
    • Nuclear Engineering and Technology
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    • v.53 no.5
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    • pp.1626-1633
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    • 2021
  • In an industrial field, non-destructive testing (NDT) is commonly used to inspect industrial products. Among NDT methods using radiation sources, X-ray laminography has several advantages, such as high depth resolution and low computational costs. Moreover, an X-ray laminography system with stationary source array and compact detector is able to reduce mechanical motion artifacts and improve inspection efficiency. However, this system, called stationary inverse-geometry X-ray laminography (s-IGXL), causes truncation artifacts in reconstructed images due to limited fields-of-view (FOVs). In this study, we proposed a projection data correction (PDC) method to reduce the truncation artifacts arisen in s-IGXL images, and the performance of the proposed method was evaluated with the different number of focal spots in terms of quantitative accuracy. Comparing with conventional techniques, the PDC method showed superior performance in reducing truncation artifacts and improved the quantitative accuracy of s-IGXL images for all the number of focal spots. In conclusion, the PDC method can improve the accuracy of s-IGXL images and allow precise NDT measurements.

A Novel Test Structure for Process Control Monitor for Un-Cooled Bolometer Area Array Detector Technology

  • Saxena, R.S.;Bhan, R.K.;Jalwania, C.R.;Lomash, S.K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.4
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    • pp.299-312
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    • 2006
  • This paper presents the results of a novel test structure for process control monitor for uncooled IR detector technology of microbolometer arrays. The proposed test structure is based on resistive network configuration. The theoretical model for resistance of this network has been developed using 'Compensation' and 'Superposition' network theorems. The theoretical results of proposed resistive network have been verified by wired hardware testing as well as using an actual 16x16 networked bolometer array. The proposed structure uses simple two-level metal process and is easy to integrate with standard CMOS process line. The proposed structure can imitate the performance of actual fabricated version of area array closely and it uses only 32 pins instead of 512 using conventional method for a $16{\times}16$ array. Further, it has been demonstrated that the defective or faulty elements can be identified vividly using extraction matrix, whose values are quite similar(within the error of 0.1%), which verifies the algorithm in small variation case(${\sim}1%$ variation). For example, an element, intentionally damaged electrically, has been shown to have the difference magnitude much higher than rest of the elements(1.45 a.u. as compared to ${\sim}$ 0.25 a.u. of others), confirming that it is defective. Further, for the devices having non-uniformity ${\leq}$ 10%, both the actual non-uniformity and faults are predicted well. Finally, using our analysis, we have been able to grade(pass or fail) 60 actual devices based on quantitative estimation of non-uniformity ranging from < 5% to > 20%. Additionally, we have been able to identify the number of bad elements ranging from 0 to > 15 in above devices.

UART-to-APB Interface Circuit Design for Testing a Chip (칩 테스트를 위한 UART-to-APB 인터페이스 회로의 설계)

  • Seo, Young-Ho;Kim, Dong-wook
    • Journal of Advanced Navigation Technology
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    • v.21 no.4
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    • pp.386-393
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    • 2017
  • Field programmable gate arrays (FPGAs) are widely used for verification in chip development. In order to verify the circuit programmed to the FPGA, data must be input to the FPGA. There are many ways to communicate with a chip through a PC and an external board, but the simplest and easiest way is to use a universal asynchronous receiver/transmitter (UART). Most recently, most circuits are designed to be internally connected to the advanced microcontroller bus architecture (AMBA) bus. In other words, to verify the designed circuit easily and simply, data must be transmitted through the AMBA bus through the UART. Also the AMBA bus has been available in various versions since version 4.0 recently. Advanced peripheral bus (APB) is suitable for simple testing. In this paper, we design a circuit for UART-to-APB interface. Circuits designed using Verilog-HDL were implemented in Altera Cyclone FPGAs and were capable of operating at speeds up to 380 MHz.

Evaluation of Microscopic Degradation of Copper and Copper Alloy by Electrical Resistivity Measurement (전기비저항 측정에 의한 구리와 구리합금의 미시적 열화평가)

  • Kim, Chung-Seok;Nahm, Seung-Hoon;Hyun, Chang-Young
    • Journal of the Korean Society for Nondestructive Testing
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    • v.30 no.5
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    • pp.444-450
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    • 2010
  • In the present study, the microscopic degradation of copper and copper alloy subjected to cyclic deformation has been evaluated by the electrical resistivity measurement using the DC four terminal potential method. The copper (Cu) and copper alloy (Cu-35Zn), whose stacking fault energy is much different each other, were cyclically deformed to investigate the response of the electrical resistivity to different dislocation substructures. Dislocation cell substructure was developed in the Cu, while the planar array of dislocation structure was developed in the Cu-35Zn alloy increasing dislocation density with fatigue cycles. The electrical resistivity increased rapidly in the initial stage of fatigue deformation in both materials. Moreover, after the fatigue test it increased by about 7 % for the Cu and 6.5 % for the Cu-35Zn alloy, respectively. From these consistent results, it may be concluded that the dislocation cell structure responds to the electrical resistivity more sensitively than the planar array dislocation structure evolved during cyclic fatigue.

Construction of Static 3D Ultrasonography Image by Radiation Beam Tracking Method from 1D Array Probe (1차원 배열 탐촉자의 방사빔추적기법을 이용한 정적 3차원 초음파진단영상 구성)

  • Kim, Yong Tae;Doh, Il;Ahn, Bongyoung;Kim, Kwang-Youn
    • Journal of the Korean Society for Nondestructive Testing
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    • v.35 no.2
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    • pp.128-133
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    • 2015
  • This paper describes the construction of a static 3D ultrasonography image by tracking the radiation beam position during the handy operation of a 1D array probe to enable point-of-care use. The theoretical model of the transformation from the translational and rotational information of the sensor mounted on the probe to the reference Cartesian coordinate system was given. The signal amplification and serial communication interface module was made using a commercially available sensor. A test phantom was also made using silicone putty in a donut shape. During the movement of the hand-held probe, B-mode movie and sensor signals were recorded. B-mode images were periodically selected from the movie, and the gray levels of the pixels for each image were converted to the gray levels of 3D voxels. 3D and 2D images of arbitrary cross-section of the B-mode type were also constructed from the voxel data, and agreed well with the shape of the test phantom.

Critical Cleaning Requirements for Flip Chip Packages

  • Bixenman, Mike;Miller, Erik
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2000.04a
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    • pp.43-55
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    • 2000
  • In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

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A Study on Development of Displacement Measurement System for Structure using a Laser and 2-D Arrayed Photo Sensors (레이저와 2차원 배열의 광전검출기를 이용한 구조물의 변위측정 시스템의 개발에 관한 연구)

  • Kang, Moon-Phil;Lee, Jin-Yi;Kim, Min-Soo;Kim, Dae-Jung;Choe, Won-Ha;Kang, Ki-Hun;Kim, Jong-Soo;Kim, Hoon
    • Journal of the Korean Society for Nondestructive Testing
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    • v.22 no.1
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    • pp.22-31
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    • 2002
  • A Safety Monitoring System using a laser and 2-D arrayed photo sensors is developed. To monitor of the deformation and small rotation of structure the developed optical system using 2-D photo sensor array was used to detect the variation of optical orbit of laser which was induced by deformation of the structure. Also, an operating program to manage the system and an algorithm for the data acquisition and the database are introduced. In this study, we demonstrated the capabilities of this system by laboratory experiments before applying the system to the field.