• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.107-111
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• 2005

As Internet grows rapidly and next electronic commerce applications increase, the security is getting more important. Information security to provide secure and reliable information transfer is based on cryptography technique. The proposed ISEED(Improved SEED) algorithm based on block cryptography algorithm which belongs to secret-key algorithm. In terms of efficiency, the round key generation algorithm has been proposed to reduces the time required in encryption and decryption. The algorithm has been implemented as follow. 128-bit key is divided into two 64-bit group to rotate each of them 8-bit on the left side and right side, and then basic arithmetic operation and G function have been applied to 4-word outputs. In the process of converting encryption key which is required in decryption and encryption of key generation algorithm into sub key type, the conversion algorithm is analyzed. As a result, the time consumed to encryption and decryption is reduced by minimizing the number of plain text required differential analysis.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.05a
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• pp.299-302
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• 2003

In fuzzy control systems having large volumes of fuzzy data. one of the important problems is the improvement of execution speed in the fuzzy inference and defuzzification stages. In this paper, to improve the speedup of fuzzy controllers, we use an integer line mapping algorithm to convert [0, 1] real values in the fuzzy membership functions to integer pixels. U sing this, we propose a real-time high-speed fuzzy control system and implement a fast fuzzy processor and control system using FPGAs.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.502-504
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• 2010

We propose novel transition rule of cellular automata for image enhancement and sharpening algorithm using it. Transition rule present sequential and parallel behavior. it also satisfy Lyapunov function. This image sharpening was developed and experimented by using a dynamic feature of convergence to fixed points. We can obtain efficiently sharpened image by performing arithmetic operation at the gradual parts of difference of brightness without image information.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.2
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• pp.241-251
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• 2015

In public-key cryptographic system based on finite field arithmetic, it is very important to challenge for implementing high speed operation. In this paper, we focused on 8-bit ATmega128 processor and concentrated on enhancing efficiency of reduction operation which uses irreducible polynomial $f(x)=x^{271}+x^{207}+x^{175}+x^{111}+1$ and $f(x)=x^{193}+x^{145}+x^{129}+x^{113}+1$. We propose optimized reduction algorithms which are designed to reduce repeated memory accesses by calculating final reduced values of Fast reduction. There are 53%, 55% improvement when proposed algorithm is implemented using assembly language, compare to previous Fast reduction algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.9
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• pp.37-43
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• 2010

An Interference Cancellation Wireless Repeater transmitts directly amplified the RF signal input to extend the coverage of the base station. Such a repeater inevitably suffers from the feedback interferences due to the environment and the adaptive Interference Cancelling System(ICS) is necessary. In this paper, the Variable Stepsize Complex Sign -Sign(VSCSS) LMS algorithm for ICS is presented. The algorithm can be implemented without multiplication/division arithmetic operation so that the required logic resources can be dramatically reduced in FPGA implementation. The performance of the proposed algorithm was analyzed in comparison with CSS-LMS algorithm and the learning curves obtained from simulation showed an excellent agreement with the theorical prediction. The simulation result with ICS in fading feedback channel environment showed the performance of the proposed algorithm is competible with NLMS algorithm.

• Speech Sciences
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• v.11 no.2
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• pp.181-192
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• 2004

This paper presents an efficient speech interactive agent rendering smooth car navigation and Telematics services, by employing embedded automatic speech recognition (ASR), distributed speech recognition (DSR) and text-to-speech (ITS) modules, all while enabling safe driving. A speech interactive agent is essentially a conversational tool providing command and control functions to drivers such' as enabling navigation task, audio/video manipulation, and E-commerce services through natural voice/response interactions between user and interface. While the benefits of automatic speech recognition and speech synthesizer have become well known, involved hardware resources are often limited and internal communication protocols are complex to achieve real time responses. As a result, performance degradation always exists in the embedded H/W system. To implement the speech interactive agent to accommodate the demands of user commands in real time, we propose to optimize the hardware dependent architectural codes for speed-up. In particular, we propose to provide a composite solution through memory reconfiguration and efficient arithmetic operation conversion, as well as invoking an effective out-of-vocabulary rejection algorithm, all made suitable for system operation under limited resources.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.195-198
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• 2013

Recognition and Tracking of interesting object is the significant field in Computer Vision. Mean-Shift algorithm have chronic problems that some errors are occurred when histogram of tracking area is similar to another area. in this paper, we propose to solve the problem. Each algorithm blocks skin color filtering, face detect and Mean-Shift started consecutive order assists better operation of the next algorithm. Avoid to operations of the overhead of tracking area similar to a histogram distribution areas overlap only consider the number of white pixels by running the Viola-Jones algorithm, simple arithmetic increases the convergence of the Mean-Shift. The experimental results, it comes to 78% or more of white pixels in the Mean-Shift search area, only if the recognition of the face area when it is configured to perform a Viola-Jones algorithm is tracking the object, was 100 percent successful.

• The KIPS Transactions:PartC
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• v.17C no.3
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• pp.233-242
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• 2010

In the recent years, power attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate results in the algorithm computations(encryption, decryption) are well-known. In case of SEED block cipher, it uses 32 bit arithmetic addition and S-box operations as non-linear operations. Therefore the masking type conversion operations, which require some operating time and memory, are required to satisfy the masking method of all non-linear operations. In this paper, we propose a new masked S-boxes that can minimize the number of the masking type conversion operation. Moreover we construct just one masked S-box table and propose a new formula that can compute the other masked S-box's output by using this S-box table. Therefore the memory requirements for masked S-boxes are reduced to half of the existing masking method's one.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.