• Title/Summary/Keyword: Arithmetic Operation Algorithm

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A Study on Constructing the Inverse Element Generator over GF(3m)

  • Park, Chun-Myoung
    • Journal of information and communication convergence engineering
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    • v.8 no.3
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    • pp.317-322
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    • 2010
  • This paper presents an algorithm generating inverse element over finite fields GF($3^m$), and constructing method of inverse element generator based on inverse element generating algorithm. An inverse computing method of an element over GF($3^m$) which corresponds to a polynomial over GF($3^m$) with order less than equal to m-1. Here, the computation is based on multiplication, square and cube method derived from the mathematics properties over finite fields.

A Fragile Watermarking Scheme Using a Arithmetic Coding (산술부호화를 이용한 연성 워터마킹 기법)

  • Piao, Cheng-Ri;Paek, Seung-Eun;Han, Seung-Soo
    • The Journal of Information Technology
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    • v.9 no.4
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    • pp.49-55
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    • 2006
  • In this paper, a new fragile watermarking algorithm for digital image is presented, which makes resolving the security and forgery problem of the digital image to be possible. The most suitable watermarking method that verifies the authentication and integrity of the digital image is the Wong's method, which invokes the hash function (MD5). The algorithm is safe because this method uses the hash function of the cryptology. The operations such as modulus, complement, shift, bitwise exclusive-or, bitwise inclusive-or are necessary for calculating the value of hash function. But, in this paper, an Arithmetic encoding method that only includes the multiplication operation is adopted. This technique prints out accumulative probability interval, which is obtained by multiplying the input symbol probability interval. In this paper, the initial probability interval is determined according to the value of the key, and the input sequence of the symbols is adjusted according to the key value so that the accumulative probability interval will depend on the key value. The integrity of the algorithm has been verified by experiment. The PSNR is above the 51.13db and the verifying time is $1/3{\sim}1/4$ of the verifying time of using the hash function (MD5), so, it can be used in the real-time system.

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New Power Analysis Attack on The Masking Type Conversion Algorithm (마스킹 형태 변환 알고리즘에 대한 새로운 전력 분석 공격)

  • Cho, Young-In;Kim, Hee-Seok;Han, Dong-Guk;Hong, Seok-Hie;Kang, Ju-Sung
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.47 no.1
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    • pp.159-168
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    • 2010
  • In the recent years, power analysis attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate results in the algorithm computations(encryption, decryption, and key-schedule) are well-known. The type conversion of masking is unavoidable since Boolean operation and Arithmetic operation are performed together in block cipher. Messerges proposed a masking type conversion algorithm resistant general power analysis attack and then it's vulnerability was reported. We present that some of exiting attacks have some practical problems and propose a new power analysis attack on Messerges's algorithm. After we propose the strengthen DPA and CPA attack on the masking type conversion algorithm, we show that our proposed attack is a practical threat as the simulation results.

A New Complex-Number Multiplication Algorithm using Radix-4 Booth Recoding and RB Arithmetic, and a 10-bit CMAC Core Design (Radix-4 Booth Recoding과 RB 연산을 이용한 새로운 복소수 승산 알고리듬 및 10-bit CMAC코어 설계)

  • 김호하;신경욱
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.9
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    • pp.11-20
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    • 1998
  • High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

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Operation of a supercritical fluid extraction process using a fuzzy expert control system (Fuzzy 전문가 제어계를 이용한 초임계 유체 추출 장치의 운전)

  • 이대욱;이광순
    • 제어로봇시스템학회:학술대회논문집
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    • 1991.10a
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    • pp.669-675
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    • 1991
  • Based on process analysis as well as extensive operation experience, two fuzzy expert control algorithms, for startup and control, are proposed for a supercritical fluid extraction process which has high interacting multivariable structure. In the proposed algorithms, a new simple defuzzification method which only requires four fundamental arithmetic rules is also presented. Through numerical simulations, control performance using the proposed control algorithm is compared with that of a different fuzzy algorithm by an other researcher and that of conventional PID-type controllers which are tuned by well-known optimal criteria. Also, the proposed control algorithm has been tested to the bench scale supercritical fluid extraction process. As a consequence, the proposed fuzzy expert controller has shown fast and robust control performance while the other controllers show sluggish and/or highly oscillatory responses.

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Improvement on Bailey-Paar's Optimal Extension Field Arithmetic (Bailey-Paar 최적확장체 연산의 개선)

  • Lee, Mun-Kyu
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.7
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    • pp.327-331
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    • 2008
  • Optimal Extension Fields (OEFs) are finite fields of a special form which are very useful for software implementation of elliptic curve cryptosystems. Bailey and Paar introduced efficient OEF arithmetic algorithms including the $p^ith$ powering operation, and an efficient algorithm to construct OEFs for cryptographic use. In this paper, we give a counterexample where their $p^ith$ powering algorithm does not work, and show that their OEF construction algorithm is faulty, i.e., it may produce some non-OEFs as output. We present improved algorithms which correct these problems, and give improved statistics for the number of OEFs.

A Fast Inversion for Low-Complexity System over GF(2 $^{m}$) (경량화 시스템에 적합한 유한체 $GF(2^m)$에서의 고속 역원기)

  • Kim, So-Sun;Chang, Nam-Su;Kim, Chang-Han
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.9 s.339
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    • pp.51-60
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    • 2005
  • The design of efficient cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. Especially, among the basic arithmetic over finite field, the rnultiplicative inversion is the most time consuming operation. In this paper, a fast inversion algerian in finite field $GF(2^m)$ with the standard basis representation is proposed. It is based on the Extended binary gcd algorithm (EBGA). The proposed algorithm executes about $18.8\%\;or\;45.9\%$ less iterations than EBGA or Montgomery inverse algorithm (MIA), respectively. In practical applications where the dimension of the field is large or may vary, systolic array sDucture becomes area-complexity and time-complexity costly or even impractical in previous algorithms. It is not suitable for low-weight and low-power systems, i.e., smartcard, the mobile phone. In this paper, we propose a new hardware architecture to apply an area-efficient and a synchronized inverter on low-complexity systems. It requires the number of addition and reduction operation less than previous architectures for computing the inverses in $GF(2^m)$ furthermore, the proposed inversion is applied over either prime or binary extension fields, more specially $GF(2^m)$ and GF(P) .

Object Tracking Using CAM shift with 8-way Search Window (CAM shift와 8방향 탐색 윈도우를 이용한 객체 추적)

  • Kim, Nam-Gon;Lee, Geum-Boon;Cho, Beom-Joon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.3
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    • pp.636-644
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    • 2015
  • This research aims to suggest methods to improve object tracking performance by combining CAM shift algorithm with 8-way search window, and reduce arithmetic operation by reducing the number of frame used for tracking. CAM shift has its adverse effect in tracking methods using signature color or having difficulty in tracking rapidly moving object. To resolve this, moving search window of CAM shift makes it possible to more accurately track high-speed moving object after finding object by conducting 8-way search by using information at a final successful timing point from a timing point missing tracking object. Moreover, hardware development led to increased unnecessary arithmetic operation by increasing the number of frame produced per second, which indicates efficiency can be enhanced by reducing the number of frame used in tracking to reduce unnecessary arithmetic operation.

An Improving Motion Estimator based on multi arithmetic Architecture (고밀도 성능향상을 위한 다중연산구조기반의 움직임추정 프로세서)

  • Lee, Kang-Whan
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.631-632
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    • 2006
  • In this paper, acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

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A Performance Improvement of QE-MMA Adaptive Equalization Algorithm based on Varying Stepsize (Varying Stepsize를 이용한 QE-MMA 적응 등화 알고리즘의 성능 개선)

  • Lim, Seung-Gag
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.1
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    • pp.101-106
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    • 2020
  • This paper relates with the VS-QE-MMA (Varying Stepsize-Quantized Error-MMA) based on the varying stepsize for improving the equalization performance in the QE-MMA adaptive equalization algorithm that is possible to reducing the intersymbol interference occurred at channel. The SE-MMA use the high-order statistics of transmitted signal and sign of error signal. The QE-MMA was appeared for the H/W implementation easiness substitutes the multiplication and substraction into the shift and substraction in the updating the tap coefficient based on the power-of-two operation of error signal magnitude. The QE-MMA gives degradation of equalization performance due to the such simplification of arithmetic operation. For improving this problem, the propose algorithm, namely VS-QE-MMA, applies the varying stepsize of the nonlinear transformation of error signal. It was confirmed by simulation that the VS-QE-MMA gives better performance than current QE-MMA in the same channel and signal to noise ratio. As a result of simulation, the VS-QE-MMA has more better performance in the every performance index, and it was also confirmed that the varying stepsize effect can be obtained in the greater than 10dB of signal to noise ratio.