• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.10
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• pp.5098-5115
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• 2017

A number of automotive electronics-safety, driver assistance, and infotainment devices-have been deployed in recent vehicles. This raises new challenges regarding in-vehicular network arbitration. A performance analysis of non-destructive arbitration has revealed a fairness issue. The arbitration prioritizes without collisions, despite multiple simultaneous transmissions; however, the performances of the highest priority node and the lowest priority node are very different. In this paper, an ID-rotation arbitration method to solve the arbitration-fairness problem is proposed. The proposed algorithm was applied to several engine control units (ECUs), including a controller area network (CAN) controller. Experimental results showed that the algorithm improved the fairness as well as the total throughput within a specific performance constraint.

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.33-36
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectric layers, which can be applied to the integrated circuits for deep sub-micron technology. The rise throughput and the stability in the device fabrication can be obtained by applying of CMP process to STI structure in 0.18$\mu\textrm{m}$ m semiconductor device. The reverse moat process has been added to employ in of each thin films in STI-CMP was not equal, hence the devices must to be effected, that is, the damage was occurred in the device area for the case of excessive CMP process and the nitride film was remained on the device area for the case of insufficient CMP process, and than, these defects affect the device characteristics. Also, we studied the High Selectivity Slurry(HSS) to perform global planarization without reverse moat step.

• Journal of the Korea Society for Simulation
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• v.3 no.1
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• pp.115-124
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• 1994

In this paper, we have developed a performance analysis tool for communication networks called COMNAS. COMNAS analyses the performance of wide area networks such as Korea Educational Network and Korea Research Environment Open Network which include local area networks such as Ethernet and Token Ring. COMNAS consists of model constructor, simulation implementor, output analyzer and user interface. Attributes of communication networks for modeling either have default values or are entered by user as object units, and implementation of simulation is automatically proceeded by user interface. Ouput results obtained by COMNAS are the status of node, link and entire network such as mean message transmission delay, throughput, utilization, and so on, and they can be selectively obtained upon the request of the user.

• Journal of Communications and Networks
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• v.16 no.3
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• pp.311-321
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• 2014

This paper focuses on contention-based medium access control (MAC) protocols used in wireless local area networks. We propose a novel MAC protocol called adaptive backoff tuning MAC (ABTMAC) based on IEEE 802.11 distributed coordination function (DCF). In our proposed MAC protocol, we utilize a fixed transmission attempt rate and each node dynamically adjusts its backoff window size considering the current network status. We determined the appropriate transmission attempt rate for both cases where the request-to-send/clear-to-send mechanism was and was not employed. Robustness against performance degradation caused by the difference between desired and actual values of the attempt rate parameter is considered when setting it. The performance of the protocol is evaluated analytically and through simulations. These results indicate that a wireless network utilizing ABTMAC performs better than one using IEEE 802.11 DCF.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.2 no.4
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• pp.171-183
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• 2008

Nowadays, wireless packet data services are provided over Wireless MAN (WMAN) at a high data service rate, while 3G cellular networks provide wide-area coverage at a low data service rate. The integration of mobile WiMAX and 3G networks is essential, to serve users requiring both high-speed wireless access as well as wide-area connectivity. In this paper, we propose a cross-layer optimization scheme for a vertical handover between mobile WiMAX and 3G cellular networks. More specifically, L2 (layer 2) and L3 (layer 3) signaling messages for a vertical handover are analyzed and reordered/combined, to optimize the handover procedure. Extensive simulations using ns-2 demonstrate that the proposed scheme enhances the performance of a vertical handover between mobile WiMAX and 3G networks: low handover latency, high TCP throughput, and low UDP packet loss ratio.

• Korean Management Science Review
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• v.19 no.1
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• pp.1-12
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• 2002

Performances of common zone with various sizes are examined for possible demand rate variations for an AS/RS. Common zone is a middle area located between the 1st class and the 2nd class to be used by the 1st class Items if the assigned racks are not enough. This area is designed to resolve the rack shortage problem associated with a particular class. In the previous researches, effect of demand rate variation is Ignored since flxed demand rate is assumed. It is found that rack shortage rate is decreased up to 67% of common zone size. However, no difference is found at above 70%. Waiting time tends to be longer with Increased common zone while travel time and throughput are not affected at all with the common zone sloe.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.9
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• pp.1652-1659
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• 2008

With the increase of huge amount of data in network systems, ultimate high-speed network has become an essential requirement. In such systems, the encryption and decryption process for security becomes a bottle-neck. For this reason, the need of hardware implementation is strongly emphasized. In this study, a mixed inner and outer round pipelining architecture is introduced to achieve high speed performance of ARIA hardware. Multiplexers are used to control the lengths of rounds for 3 types of keys. Merging of encryption module and key initialization module increases the area efficiency. The proposed hardware architecture is implemented on reconfigurable hardware, Xilinx Virtex2-pro. The hardware architecture in this study shows that the area occupied 6437 slices and 128 BRAMs, and it is translated to throughput of 24.6Gbit/s with a maximum clock frequency of 192.9MHz.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.34 no.6
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• pp.569-578
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• 2016

With the recent advancement of surveying and technology, the spatial data acquisition rates and precision have been improved continually. As the updates of spatial data are rapid, and the size of data increases in line with the advancing technology, the LOD (Level of Detail) algorithm has been adopted to process data expressions in real time in a streaming format with spatial data divided precisely into separate steps. The existing GRID analysis utilizes the single DEM, as it is, in examining and analyzing all data outside the analysis area as well, which results in extending the analysis time in proportion to the quantity of data. Hence, this study suggests a method to reduce analysis time and data throughput by acquiring and analyzing DEM data necessary for GRID analysis in real time based on the area of analysis and the level of precision, specifically for streaming DEM data, which is utilized mostly for 3D geographic information service.