• International Journal of Naval Architecture and Ocean Engineering
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• 제2권4호
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• pp.211-216
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• 2010

Recently a Wide Chord Tip (WCT) propeller has been developed and applied to a commercial ship by STX Offshore & Shipbuilding. It is reported that the WCT propeller significantly reduces pressure fluctuations and also ship's noise and vibration. On the sea trial, vibration magnitude in the accommodations at NCR was measured at 0.9mm/sec which is only 10% of international allowable magnitude of vibration (9mm/sec). In this paper, a design method for increasing performance of the marine propellers including the WCT propeller is suggested. It is described to maximize the performance of the propeller by adjusting expanded areas of the propeller blade. Results show that efficiency can be increased up to over 2% through the suggested design method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.736-744
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• 2016

Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

• 한국정보처리학회논문지
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• 제5권4호
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• pp.873-882
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• 1998

현재 병렬 데이타베이스 컴퓨터가 광범위하고 성공적으로 활용되고 있다. 이의 구조로는 주기억 장치와 디스크를 공유하지 않는 구조, 두가지를 모두 공유하는 구조, 디스크만을 공유하는 구조, 그리고 절충형 구조 등의 네가지 구조가 있다. 이 논문에서는 데이타베이스 컴퓨터 구조의 성능을 비교 분석하기 위하여 데이타베이스 컴퓨터 구조를 추상적인 모형으로 정의하고, 각각의 모형에 대하여 절충형 해쉬 조인 연산의 수행시간을 수식화한 성능식을 구하여 여러 가지 데이타베이스 컴퓨터 구조 모형의 수행시간을 비교 분석한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.284-299
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• 2014

Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA-based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.

• 한국해양공학회지
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• 제30권6호
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• pp.431-439
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• 2016

This paper reports a numerical method for determining the resistance and self-propulsion performance of an asymmetric pre-swirl stator used as an energy saving device by cancelling a propeller's rotational energy. The present asymmetric pre-swirl stator propulsion system consists of three blades at the port and one blade at the starboard, which can effectively recover the biased rotating flow. This paper provides the design concept for the present asymmetric stator, which produces more efficient results than a conventional propeller.

• Steel and Composite Structures
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• 제47권1호
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• pp.121-134
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• 2023

This paper tested 11 concrete-encased concrete-filled steel tube (CFST) composite columns and one reinforced concrete column under combined axial compression and lateral loads. The primary parameters, including the loading system, axial compression ratio, volume stirrup ratio, diameter-to-thickness ratio of the steel tube, and stirrup form, were varied. The influence of the parameters on the failure mode, strength, ductility, energy dissipation, strength degradation, and damage evolution of the composite columns were revealed. Moreover, a two-parameter nonlinear seismic damage model for composite columns was established, which can reflect the degree and development process of the seismic damage. In addition, the relationships among the inter-story drift ratio, damage index and seismic performance level of composite columns were established to provide a theoretical basis for seismic performance design and damage assessments.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제16권9호
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• pp.2882-2903
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• 2022

Image super-resolution (SR) processing is of great value in the fields of digital image processing, intelligent security, film and television production and so on. This paper proposed a densely connected deep learning network based on cascade architecture, which can be used to solve the problem of super-resolution in the field of image quality enhancement. We proposed a more efficient residual scaling dense block (RSDB) and the multi-channel cascade architecture to realize more efficient feature reuse. Also we proposed a hybrid loss function based on L₁ error and L_∞ error to achieve better L_∞ error performance. The experimental results show that the overall performance of the network is effectively improved on cascade architecture and residual scaling. Compared with the residual dense net (RDN), the PSNR / SSIM of the new method is improved by 2.24% / 1.44% respectively, and the L_∞ performance is improved by 3.64%. It shows that the cascade connection and residual scaling method can effectively realize feature reuse, improving the residual convergence speed and learning efficiency of our network. The L_∞ performance is improved by 11.09% with only a minimal loses of 1.14% / 0.60% on PSNR / SSIM performance after adopting the new loss function. That is to say, the L_∞ performance can be improved greatly on the new loss function with a minor loss of PSNR / SSIM performance, which is of great value in L_∞ error sensitive tasks.

• 한국멀티미디어학회논문지
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• 제8권12호
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

• 한국조경학회:학술대회논문집
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• 한국조경학회 2015년도 추계학술대회 논문집
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• pp.101-102
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• 2015