• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.11-20
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• 1994

We propose two architectures using two dimensional systolic arrays for the DCT/DST/DHT. One decomposes the N-point DCT/DST/DHT into even-and odd-numbered frequency samples, and then computes them independently at the same time. In addition, the proposed architecture can be used for the IDCT/IDST/IDHT. Anogher is the modified version for the DHT/IDHT. Two proposed architectures generate outputs sequentially using real multiplications and additions. As compared to the conventional methods the proposed systolic arrays exhibit many advantages in terms of simplicity of the processing element (PE), latency, and throughput. Teh simulation results using VHDL, international standard language for hardware description, show the effectiveness of the proposed architecture.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.209-210
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• 2011

In this paper, an area-efficient architecture of LDPC Decoder is proposed for DVB (Digital Video Broadcasting) 2.0 systems. The proposed LDPC Decoder was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of slices for the decoder is 56122 and the number of block RAM is 135.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.212-226
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• 2014

This paper presents the design and implementation of a pipelined architecture and a method for real-time human detection using depth image from a Time-of-Flight (ToF) camera. In the proposed method, we use Euclidean Distance Transform (EDT) in order to extract human body location, and we then use the 1D, 2D scanning window in order to extract human joint location. The EDT-based human extraction method is robust against noise. In addition, the 1D, 2D scanning window helps extracting human joint locations easily from a distance image. The proposed method is designed using Verilog HDL (Hardware Description Language) as the dedicated hardware architecture based on pipeline architecture. We implement the dedicated hardware architecture on a Xilinx Virtex6 LX750 Field Programmable Gate Arrays (FPGA). The FPGA implementation can run 80 MHz of maximum operating frequency and show over 60fps of processing performance in the QVGA ($320{\times}240$) resolution depth image.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.3
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• pp.79-94
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• 1997

OMG (Object Management Group) published a security service specification, called CORBA (Common Object Request Broker Architecture) security reference model because the integration of security and object-oriented techniques was critical for successful deployment of distributed object systems. The CORBA security reference model treats access control as an implementation independent semantic concept but has incomplete semantics of the access control function. Because of such imcompleteness it is difficult for the system administrator and the CORBA security implementor to have the same understanding for the meaning of access control in the CORBA security. We propose a formal model for access control the CORBA security using the formal description language, which is called Z language based on typed set theory. The proposed model provides concrete semantics of the access control function to both the system administrator and the implementor.

• Nuclear Engineering and Technology
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• v.40 no.5
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• pp.365-374
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• 2008

Dependability-critical systems, such as digital instrumentation and control systems in nuclear power plants, necessitate engineering techniques and tools to provide assurances of their safety and reliability. Determining system reliability at the architectural design phase is important since it may guide design decisions and provide crucial information for trade-off analysis and estimating system cost. Despite this, reliability and system engineering remain separate disciplines and engineering processes by which the dependability analysis results may not represent the designed system. In this article we provide an overview and application of our approach to build architecture-based, dynamic system models for dependability-critical systems and then automatically generate dynamic fault trees (DFT) for comprehensive, tool-supported reliability analysis. Specifically, we use the Architectural Analysis and Design Language (AADL) to model the structural, behavioral and failure aspects of the system in a composite architecture model. From the AADL model, we seek to derive the DFT(s) and use Galileo's automated reliability analyses to estimate system reliability. This approach alleviates the dependability engineering - systems engineering knowledge expertise gap, integrates the dependability and system engineering design and development processes and enables a more formal, automated and consistent DFT construction. We illustrate this work using an example based on a dynamic digital feed-water control system for a nuclear reactor.

• Journal of Intelligence and Information Systems
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• v.11 no.2
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• pp.105-121
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• 2005

To realize a ubiquitous logistics management system using the smart object of Electronic Product Code(EPC) enabled RFID tag, the design and management of RFID Information Service is very important. RFID Information Service searches, transfers and responds to the other's PML request, but Physical Markup Language (PML) data management between trading system elements has issues of standardization of PML data description and processing, and problems of data traffic and communication time overload because of the innate distributed characteristics. As a complementary study, this research analyzes the usage patterns and data types of PML. On that analysis we provide a design of the distributed RFID Information Service architecture of PML data management that is using DB middleware. Standalone and Integrated type of RFID IS were proposed.

• The KIPS Transactions:PartC
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• v.8C no.1
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• pp.32-40
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• 2001

In this paper, we propose a high-speed modular multiplication algorithm which revises conventional Montgomery's algorithm. A hardware architecture is also presented to implement 1024-bit RSA cryptosystem for digital signature based on the proposed algorithm. Each iteration in our approach requires only one addition operation for two n-bit integers, while that in Montgomery's requires two addition operations for three n-bit integers. The system which is modelled in VHDL(VHSIC Hardware Description Language) is simulated in functionally through the use of $Synopsys^{TM}$ tools on a Axil-320 workstation, where Altera 10K libraries are used for logic synthesis. For FPGA implementation, timing simulation is also performed through the use of Altera MAX + PLUS II. Experimental results show that the proposed RSA cryptosystem has distinctive features that not only computation speed is faster but also hardware area is drastically reduced compared to conventional approach.

• The Journal of Engineering Research
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• v.6 no.1
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• pp.111-124
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• 2004

The advanced semiconductor technology and electronic design automation(EDA) tools make it possible to implement the system on the programmable logic devices. The electronic design method is also changing from schematic capture to hardware description language. In this paper, I present the architecture of multi-dimensional digital filter which can be efficiently implemented on PLDs. This is based on the former research results which are called algorithm decomposition technique. Algorithm decomposition technique is used to obtain the computational primitive from the state space equations of the multi-dimensional digital filtering algorithm. The obtained computational primitive is designed with VHDL. This can be used to implement the filtering system as a component. The designed filtering system is implemented on the PLD. Therefore, the filter can be upgradable on system. It is greatly reduced the time-to-market time of the system that is based on the multi-dimensional filter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.6
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• pp.1101-1105
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• 2006

Ubiquitous computing network comprises a variety of distributed service devices. Today Web services technology enables the heterogeneous devices to provide their own services and interact with each other via well-defined Internet protocol. Nevertheless, service devices in ubiquitous environments require more event-driven, autonomous interaction beyond rather passive service-oriented architecture of the present time. This paper presents an ECA (Event-Condition-Action) rule description language in an attempt to support capability for autonomous interactions among service-oriented devices in ubiquitous computing network. Specifically, the proposed WS-ECA is an XML-based ECA rule description language for web service-enabled devices. The rules are embedded in distributed devices which invoke appropriate services in the network if the rules are triggered by some internal or external events. The presented ECA-based device coordination approach is expected to facilitate seamless inter-operation among the web service-enabled devices in the emerging ubiquitous computing environment.

• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.