• Speech Sciences
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• v.14 no.4
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.6
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• pp.372-377
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• 2003

Many of modem radars use modulated pulse repetition intervals for the purpose of anti-aliasing and ECCM. The interception, analysis and identification of radar signals is a major function of a radar intercept receiver. In this paper, we discuss the identification of pulse repetition intervals modulation of radar signals which is one of the major parameters for the analysis of radar. We proposed a new algorithm based on Markov models approach. This approach is shown to be reliable and robust to the missing pulses, as well as to require only relatively few pulse data.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.34-37
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• 2001

This paper presents some results after comparing the characteristics of 3 algorithms, which are discrete Fourier transform based algorithm, least square method, and modified differential approximation algorithm, used at most distance relays all over the world. In case of the DFT based distance relaying algorithm, the length of the algorithm data window and the cut-off frequency of an anti-aliasing low-pass filter adopted are fixed. On the other hand, the data window lengths are changed according to the corresponding low-pass filters in the rest two algorithms. In series of tests, the apparent impedance estimated by the modified differential approximation algorithm shows faster and more stable characteristics of convergence than the two others.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2006.06a
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• Korean Journal of Computational Design and Engineering
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• v.10 no.2
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• pp.107-113
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• 2005

Octree-based algorithm is developed for machining simulation. Most of commercial machining simulators are based on Z map model, which have several limitations to get a high precision in 5 axis machining simulation. Octree representation is three dimensional decomposition method. So it is expected that these limitations be overcome by using octree based algorithm. By using the octree model, storage requirement is reduced. And also recursive subdivision was processed in the boundaries, which reduces useless computation. The supersampling method is the most common form of the anti-aliasing and usually used with polygon mesh rendering in computer graphics. Supersampling technique is applied for advancing its efficiency of the octree algorithm.

• Bulletin of the Korean Space Science Society
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• 2004.10b
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• pp.337-340
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• 2004

Upper stage telemetry system of KSLV- I (Korea Space Launch Vehicle I) is composed of MDU (Master Data Unit), RDU (Remote Data Unit), SRU (Shock Recorder Unit) and Transmitter. RDU is the front-end telemetry data acquisition unit which gathers analog/discrete signals from various sensors and other units, and transmits the processed data to MDU via MIL-STD-I553B data bus. In order to acquire useful data from analog signal, signal conditioning circuits, such as anti-aliasing or amplifying, should be implemented. For this purpose, SCM (Signal Conditioning Module) had been developed. This paper describes hardware structure of SCM and analog signal conditioning circuits for various sensors. Also, sampling time scheme for different sampling rates were designed and tested.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.5
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• pp.711-720
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• 1994

A distance relaying algorithm for detecting faults at power transmission line is presented in this paper. The algorithm is based on differential equation from relaton between voltage and current, which is composed of lumped resistance and inductance. During the fault transient state,the voltage and current signals are severely distorted due to the exponentially decaying DC offset and high frequency components, In spite of using small data, the presented integral method to evaluate R and L from voltage and current has high performance against these harmonics including DC offset. Therefore, the presented algorithm can be implemented with only a low order anti-aliasing analog filter and dosen't need any digital filter to remove specific components.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.944-949
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• 1986

By improving the ability of arithmatic processing with an arithmatic processor in a microcomputer and realizing the data input system for real time analysis, an FFT analyzer that is usable within the range of audio frequency is designed and constructed. The input signal passes through a gain programmable pre-amplifier and anti-aliasing lowpass filter into an analogditital converter to be converted into digital form. The converted input data is processed by an Apple II microcomputer. The results of the processing are displayed using a microcomputer display unit and can be copied on a printer or stored in a floppy disk.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.51 no.10
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• pp.495-501
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• 2002

A difference based current transformer (CT) saturation detection algorithm uses the third difference of a secondary current to detect the instants of the beginning/end of saturation. The third difference of a secondary current contains high frequency components when a CT is saturated. Thus, an effect of an anti-aliasing lowpass filter implemented in digital protection relays on the detection algorithm should be studied. This paper describes performance analysis of a lowpass filter on the CT saturation detection algorithm. The cutoff frequency of the lowpass filter is normally set to be half of a sampling frequency. In this Paper, two sampling frequencies of 3,840 (Hz) corresponding to 64 sample/cycle (s/c) and 1,920 (Hz) corresponding to 32 (s/c) are studied; the cutoff frequencies of the lowpass filters are set to be 1,920 (Hz), 960 (Hz) and 960(Hz), 480(Hz), respectively. And the proposed algorithm is verified by experiment. A 2nd order Butterworth filter is designed as a lowpass filter. The test results and experiment results clearly indicate that the saturation detection algorithm successfully detects the instants of the beginning/end of saturation even though a secondary current is filtered by the designed lowpass filters.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.309-311
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• 2014

The tile-based rendering technique which divides the screen area into tiles of a specific size and creates a 3D graphic model of one tile at a time is used to efficiently utilize limited resources in a 3D graphic pipeline. In this paper, the tiling speed of tile-based rendering was improved by reducing the count of calling lower-levels in the hierarchical tile-based rendering technique. The tiling speed of the proposed Rasterizer is 13.030ms which is 56% faster than 29.614ms of multi-sort tiling and 24% faster than 17.208ms of the conventional hierarchical tiling technique.