• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.91-99
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• 1994

Damage induced by Si ion implantation and its annealing behavior during rapid thermal annealing were investigated by cross-sectional TEM (transmission electron microscopy) and RB ( Rutherford backscattering) spectrum. 150keV and 50keV Si ions were implanted in Si (100) at room temperature with doses of 2${\times}10^{15}cm^{-2}$. And 100keV Si ions were implanted in Si with doses from 1${\times}10^{14}cm^{-2}$. A variety of damage structures were generated by Si ion implantation such as continuous amorphous layer extending to the surface buried amorphous layer and damage clusters. Damage clusters are annealed out at the lower annealing temperature of 550 $^{\circ}C$. However, event at the temperature of 110$0^{\circ}C$ end of range loops remain in the original lower amorphous/crystal interface in the case of continuous and buried amorphous layer formation. Extended defects in the shape of zipper dislocations are also observed at the middle of the recrystallized region in the buried amorphous layer.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.55-57
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• 2017

Amorphous oxide thin film transistors (TFTs) were fabricated with 0.5 wt% silicon doped zinc tin oxide (a-0.5SZTO) thin film deposited by radio frequency (RF) magnetron sputtering. In order to investigate the effect of annealing treatment on the electrical properties of TFTs, a-0.5SZTO thin films were annealed at three different temperatures ($300^{\circ}C$, $500^{\circ}C$, and $700^{\circ}C$ for 2 hours in a air atmosphere. The structural and electrical properties of a-0.5SZTO TFTs were measured using X-ray diffraction and a semiconductor analyzer. As annealing temperature increased from $300^{\circ}C$ to $500^{\circ}C$, no peak was observed. This provided crystalline properties indicating that the amorphous phase was observed up to $500^{\circ}C$. The electrical properties of a-0.5SZTO TFTs, such as the field effect mobility (${\mu}_{FE}$) of $24.31cm^2/Vs$, on current ($I_{ON}$) of $2.38{\times}10^{-4}A$, and subthreshold swing (S.S) of 0.59 V/decade improved with the thermal annealing treatment. This improvement was mainly due to the increased carrier concentration and decreased structural defects by rearranged atoms. However, when a-0.5SZTO TFTs were annealed at $700^{\circ}C$, a crystalline peak was observed. As a result, electrical properties degraded. ${\mu}_{FE}$ was $0.06cm^2/Vs$, $I_{ON}$ was $5.27{\times}10^{-7}A$, and S.S was 2.09 V/decade. This degradation of electrical properties was mainly due to increased interfacial and bulk trap densities of forming grain boundaries caused by the annealing treatment.

• Journal of Korean Vacuum Science & Technology
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• v.6 no.2
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• pp.79-83
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• 2002

As Ag does not form my silicide on Si surfaces, Ag wire is a candidate for self-assembled nanowire on the reconstructed and single-domain Si(5 5 12)-2 $\times$ 1. In the present study, various Ag coverages and post-annealing temperatures had been tested to fabricate a Ag nanowire with high aspect ratio. When Ag coverage was less than 0.03 ML and the post-annealing temperature was 500(C, Ag atoms preferentially adsorbed on the tetramer sites resulting in Ag wires with an inter-row spacing of ~5 nm. However, its aspect ratio is relatively small and its height is also not even. On the other hand, the Ag-posited surface completely loses its reconstruction even with the same annealing at 500 $\^{C}$ if the initial coverage exceeds 0.05 ML. But the additional subsequent annealing at 700$\^{C}$ and slow-cooling process recovers the well-ordered Ag chain with relatively high aspect ratio on the same tetramer sites. It can be understood that, in the double step annealing process, the lower temperature annealing is required for cohesion of adsorbed Ag atoms and the higher temperature annealing is for providing Ag atoms to the tetramer sites.

• Journal of the Korean Vacuum Society
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• v.7 no.4
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• pp.293-299
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• 1998

We have investigated the atomic and electronic structures of Cu-adsorbed Si(100)-2$\times$1 surface, by using LEED and UPS. In the UPS spectra, the weak structures (peaks) related to Cu silicide appeared for low coverages less than 1.3 ML at room temperature, and the intensity of Cu 3d band rapidly increased with respect to Cu coverages. The Cu silicide peaks become clear after Cu deposition at room temperature followed by high temperature annealing ($\geq 300^{\circ}C$) or for Cu deposited surface at the substrate temperature of $400^{\circ}C$. On the other hand, these structures disappeared by annealing at $750^{\circ}C$. At very low coverage, a surface state near Fermi level $(E_F)$ was observed at $400^{\circ}C$. According to the rigid band model, it seems to be originated from the surface empty state occupied partially with Cu 4s electron. In the LEED patterns, no Cu-induced superstructure observed for RT-depositions and post annealing, while there were several surface structures which depend on substrate temperatures and coverages. we observed the clean surface 2$\times$1+2$\times$2 phase for 1.5 ML at $400^{\circ}C$, the clean surface 2$\times$1+5$\times$1 phase for 0.5 ML at $450^{\circ}C$ and the clean surface 2$\times$1+2$\times$2+5$\times$2+5$\times$5+10$\times$2 mixed phases for 3 ML at $450^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.371-372
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• 2012

We have studied lead-based gapless semiconductors, $PbPdO_2$, which is very sensitive to external parameters such as temperature, pressure, electric field, etc[1]. We have fabricated pure $PbPdO_2$, Co- and Mn-doped $PbPdO_2$ thin films using the pulsed laser deposition. Because of the volatile element of Pb, it is very difficult to grow the films. Note that in case of $MgB_2$, Mg is also volatile element. So in order to enhance the quality of $MgB_2$, some experiments are carried out in annealing with Mg-rich atmosphere [2]. This annealing process with volatile element plays an important role in making smooth surface. Thus, we applied such process to our studies of $PbPdO_2$ thin films. As a result, we found the optimal condition of ex-situ annealing temperature ${\sim}650^{\circ}C$ and time ~12 hrs. The ex-situ annealing brought the extreme change of surface morphology of thin films. After ex-situ annealing with PbO-rich atmosphere, the grain size of thin film was almost 100 times enlarged for all the thin films and also the PbO impurity phase was smeared out. And from X-ray diffraction measurements, we determined highly crystallized phases after annealing. So, we measured electrical and magnetic properties. Because of reduced grain boundary, the resistivity of ex-situ annealed samples changed smaller than no ex-situ sample. And the carrier densities of thin films were decreased with ex-situ annealing time. In this case, oxygen vacancies were removed by ex-situ annealing. Furthermore, we will discuss the transport and magnetic properties in pure $PbPdO_2$, Co- and Mn-doped $PbPdO_2$ thin films in detail.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.161-165
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• 1993

The geometrical and electronic structure of epitaxially grown Ge on Si(100) and Si(111) surfaces has been studied by scanning tunneling microscopy. Since Ge atoms could be distinguished from Si atoms by scanning tunneling spectroscopy and voltage dependent STM images, the growth mode of the added layer could be studied. On the (100) surface with a (2${\times}$1) reconstruction, Ge overlayer grow preferentially on the B type step edges at 720K. On the (111) surface, Ge overlayer also grow on the step edges with (7${\times}$7) and (5${\times}$5) structure depending on their coverage and annealing temperature.

• Korean Journal of Materials Research
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• v.14 no.8
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• pp.552-557
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• 2004

Thin Ni-B films, 1 ${\mu}m$ thick, were electrolessly deposited on Cu bus electrode fabricated by electro deposition. The purpose of these films is to encapsulate Cu electrodes for preventing Cu oxidation and to serve as a diffusion barrier against copper contamination of dielectric layer in AC-plasma display panel. The layers were heat treated at $580^{\circ}C$(baking temperature of dielectric layer) with and without pre-annealing at $300^{\circ}C$($Ni_{3}B$ formation temperature) for 30 minutes. In the layer with pre-annealing, amount of Cu diffusion was lower about 5 times than that in the layer without pre-annealing. The difference of Cu concentration could be attributed to Cu diffusion before $Ni_{3}B$ formation at grain boundaries. However, the diffusion behavior of the layer with pre-annealing was similar to that of the layer without pre-annealing after $Ni_{3}B$ formation. With increasing annealing time, Cu concentration of both layers increased due to grain growth.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.3
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• pp.126-134
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• 1996

Tungsten silicide films were deposited on the phosphorus-doped poly-Si/SiO$_{2}$/Si-substrates by LPCVD (low pressue chemical vapor deposition). The formation and various properties of tungsten silicide processed by furnace annealing in N$_{2}$ ambient were evaluated by using XRD. AFM, 4-point probe and SEM. And the redistribution of phosphorus atoms has been observed by SIMS. The crystal structure of the as-deposited tungsten silicide films were transformed from the hexagonal to the tetragonal structure upon annealing at 550.deg. C. The surface roughness of tungsten polycide films were found to very smoothly upon annelaing at 850.deg. C and low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide films are measured to be 2.4 .ohm./ㅁafter furnace annealing at 1100.deg. C, 30min. It was found that the sheet resistance of tungsten polycide films upon annealing above 1050.deg. C were independant on the phosphorus concentration of polysilicon layer and furnace annealing times. An out-diffusion of phosphorus impurity through tungsten silicide film after annealing in $O_{2}$ ambient revealed a remarkably low content of dopant by oxide capping.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.207-213
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• 2003

The Sr$\_$0.7/Bi$\_$2.6/Ta$_2$O$\_$9/(SBT) thin films are deposited on Pt-coated electrode(Pt/TiO$_2$/SiO$_2$/Si) using RF magnetron sputtering method. The structural and electrical properties of SBT capacitors were influenced with annealing atmosphere. In the XRD pattern, the SBT thin films in all annealed atmosphere had (105) orientation. In the SEM images, Bi-layered perovskite phase was crystallized in all annealing atmosphere and grain largely grew in oxygen annealing atmosphere. The maximum remnant polarization and the coercive electric field in oxygen annealing atmosphere are 12.40[${\mu}$C/cm$^2$] and 30[kV/cm] respectively. The dielectric constant and leakage current density of capacitors annealed oxygen atmosphere are 340 and 2.13${\times}$10$\^$-9/ [A/cm$^2$] respectively. The fatigue characteristics of SBT capacitors did not change up to 10$\^$10/ switching cycles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.9
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• pp.739-743
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• 2011

Ga doped ZnO (GZO)/Cu bi-layer films were deposited with RF and DC magnetron sputtering on glass substrate and then the effect of post deposition annealing temperature on the structural, optical and electrical properties of the films was investigated. The post deposition annealing process was conducted for 30 minutes in gas pressure of $1{\times}10^{-3}$ Torr and the annealing temperatures were 150 and $300^{\circ}C$. With increasing annealing temperature, GZO/Cu films showed an increment in the prefer orientation of ZnO (002) diffraction peak in the XRD pattern and the optical transmittance in a visible wave region was also increased, while the electrical sheet resistance was decreased. The GZO/Cu films annealed at $300^{\circ}C$ showed the highest optical transmittance of 70% and also showed the lowest electrical resistance of $85\;{\Omega}/{\Box}$ in this study.