• 전자공학회논문지C
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• 제35C권9호
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• pp.57-63
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• 1998

본 논문에서는 새로운 디지털-아날로그 변환알고리즘을 적용한 CMOS 디지털-아날로그 변환기를 개발하였다. 이 변환기를 1.2㎛ MOSIS SCMOS 파라미터로 설계하여 시뮬레이션으로 그 성능을 확인해 본 결과 200MHz의 최대변환속도와 7.41mW의 DC 소모전력을 나타내었고 8-b에서 각각 ±0.008LSB의 INL(integral nonlinearity)과 ±0.098LSB의 DNL(differential nonlinearity)를 나타내었다.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1986년도 추계학술발표회 논문집
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• pp.68-71
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• 1986

A new circuit configuration for charge-balancing successive approximation Analog-to-Digital converters is described. This consists of a improved successive approximation register(SAR) and a weighted capacitor Digital-to-Analog converter (WCDAC). Due to the inherent conversion property of the WCDAC, the A/D converter using the WCDAC can be simply implemented by successive approximation conversion method, and 4bit monotonicity conversion with differential nonlinearity less 1/2LSB is completed in 80 US.

• 한국음향학회지
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• 제16권2호
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• pp.80-88
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• 1997

본 연구는 현재 디지탈 방식의 이동통신에서 사용되는 디지탈/아날로그 겸용 단말기에서 아날로그 방식을 지원하기 위한 오디오/데이타 프로세서를 ETRI DSP를 이용하여 실시간 구현하는 것에 대한 것이다. 오디오/데이타 프로세서는 단말기가 아날로그 방식으로 동작할 때 광대역 데이타 처리, 오디오신호 처리 및 demodulation, data rate conversion 기능을 수행한다. 이와같은 기능은 어셈블리 언어로 프로그램되어 디지탈 방식에서 사용되는 보코더 프로그램과 함께 ETRI DSP에 탑재되었다. 즉 하나의 하드웨어를 이용하여 디지탈 방식의 보코더와 아날로그 방식의 오디오/데이타 프로세서를 함께 구현 함으로써 하드웨어의 효율성을 극대화 하여 기존의 아날로그 전용의 단말기와의 경쟁력을 가질 수 있도록 하였다.

• ETRI Journal
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• 제46권2호
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• pp.238-249
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• 2024

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.

• 대한전기학회논문지
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• 제38권10호
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• pp.795-804
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• 1989

A parallel analog-to digital converter with neuron-like elements is designed and optically implemented. Its operation principle is based on the simultaneous estimation of bit values for a given analog input. The architecture of the proposed analog-to-digital converter is simpler than that of an earlier one designed by the energy minimization technique, and its digital output is independent of the initial state. Mixed binary-to-full binary converters are also designed by using out analog-to-digital converters as basic computing elements. These converters have simple structures and fast conversion times compared with earlier ones.

• 대한전자공학회논문지
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• 제27권8호
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• pp.1255-1259
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• 1990

A new ripple analog-to-digital converter (ADC) has been developed. It consists of two parallel ADCs and a switching network. The circuit operates on the analog input signal in two serial steps. First, a coarse conversion is made to determine the most significant bits by the first parallel ADC. The resultant bits control the switching network to connect a series resistor segment, within which the analog signal is contained, to the second parallel ADC. At second step, a fine conversion is made to determine the least significant bits by the second parallel ADC. The circuit requires 2(2\ulcorner\ulcorner1) comparators, 2(2\ulcorner\ulcorner resistors, and 2(2\ulcorner\ulcorner swithches for N-bit resolution.

• 문화기술의 융합
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• 제4권4호
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• pp.379-385
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• 2018

본 논문은 절연된 환경에서 멀티채널 아날로그 신호의 정확하고 안전한 전송을 위해 옵토커플러를 활용한 신호의 전송과 절연에 대해 다룬다. 신호의 전송 과정에서 절연 소자의 온도 의존성과 비선형성에 의한 신호의 왜곡을 최소화하고 우수한 잡음 여유도를 확보하기 위해 디지털 절연을 이용한 디지털 전송을 연구한다. 옵토커플러를 적용한 디지털 전송에 대한 이론적 고찰을 토대로 멀티채널 아날로그 신호의 전송 회로를 제안하였고 디지털 데이터의 직렬 전송 프레임도 설계하였다. 이론적 고찰과 일치하는 실험 결과를 통하여 제안하는 회로와 구현된 프로그램이 절연 장벽을 극복하고 멀티채널 아날로그 신호를 정확히 전송할 수 있음을 증명하였다.

• 한국통신학회논문지
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• 제22권2호
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• pp.306-317
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• 1997

This ppaer presents a bit-rate conversion system for efficient communications between 3 channel CVSD systems with different bit-rates. The proposed conversion system is implemented in the digital domain and specially, the conversion problem between 32 Kbps and 16 Kbps CVSD systems is studied. The conventional conversion system implemented in the analog domain allows signals to be easily degraded by external noises. To overcome this problem, a digital CVSD bit-rate conversion system robust to external noises is developed. the new systemdecodes CVSD bit sequences and converts sampling rates of decoded signals, then encodes signals at target bit-rates. Since linear phase property does not matter in this application, instead of FIR filters a IIR filter is employed to reduce the system complexity. Therefore, a 3 channel digital CVSD bit-rate conversion system was successfully real-time implemented using a general purpose DSP. In addition, conversion problems with unkown time constants were experimented and good experimental results were obtained.