• Title/Summary/Keyword: Analog neuron

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CMOS Synaptic Model Considering Spatio-Temporal Summation of lnputs

  • Fujita, Takeshi;Matsuoka, Jun;Saeki, Katsutoshi;Sekine, Yoshifumi
    • Proceedings of the IEEK Conference
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    • 2002.07b
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    • pp.1188-1191
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    • 2002
  • A number of studies have recently been published concerning neuron models and asynchronous neural networks. In the case of large-scale neural networks having neuron models, the neural network should be constructed using analog hardware, rather than by computer simulation via software, because of the limitation of the computational power, In this paper, we discuss the circuit structure of a synaptic section model having the spatio-temporal summation of inputs and utilizing CMOS processing.

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The Role of Survival Motor Neuron Protein associated with Function of Spinal Motor Neuron (척수 운동신경원의 기능과 관련된 생존운동신경원 단백질의 역할)

  • Song, Ju-Young;Kown, Young-Shil;Nam, Ki-Won;Song, Ju-Min;Kim, Dong-Hyun;Kim, Suk-Bum;Moon, Dong-Chul;Choi, Ji-Ho;Kim, Jin-Sang
    • The Journal of Korean Physical Therapy
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    • v.13 no.2
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    • pp.433-444
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    • 2001
  • This review highlights the ontogenesis and the differentiation of motor neuron in spinal cord, and introduce the survival motor neuron(SMN) which is associated with growth and survival of motor neurons. The differentiation of floor plate cells and motor neurons in the vertebrate neural tube appears to be induced by signals from the notochord. This signal is Sonic hedgehog(Shh). The early development of motor neurons involves the inductive action of Shh. The SMN gene is essential for embryonic viability. SMN mRNA is also expressed in virtually all cell types in spinal cord, including large motor neurons. The SMN protein is involved in RNA processing and during early embryonic development is necessary fer cell survival. Two SMN genes are present in 5q 13 in humans: the telomeric gene(SMNt), which is the SMA-determining gene, and the centromeric analog gene(SMNc). The majority of transcripts from the SMNt gene are full length but, major transcripts of the SMNc gene have a high degrees of alternative splicing and tend to have little or no exon 7. The SMN is involved in the RNA processing(the biogenesis of snRNPs and pre-mRNA splicing), the anti-apoptotic effects, and regulating gene expression.

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A Study of a High Performance Capacitive Sensing Scheme Using a Floating-Gate MOS Transistor

  • Jung, Seung-Min
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.194-199
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    • 2012
  • This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

Memristor Bridge Synapse-based Neural Network Circuit Design and Simulation of the Hardware-Implemented Artificial Neuron (멤리스터 브리지 시냅스 기반 신경망 회로 설계 및 하드웨어적으로 구현된 인공뉴런 시뮬레이션)

  • Yang, Chang-ju;Kim, Hyongsuk
    • Journal of Institute of Control, Robotics and Systems
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    • v.21 no.5
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    • pp.477-481
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    • 2015
  • Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

A Study on the Synaptic Characteristics of SONOS memories for the Artificial Neural Networks (인공신경망을 위한 SONOS 기억소자의 시냅스특성에 관한 연구)

  • 이성배;김주연;서광열
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.1
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    • pp.7-11
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    • 1998
  • In this paper, a new synapse cell with nonvolatile SONOS semiconductor memory device is proposed and it's fundamental function electronically implemented SONOS NVSM has shown characteristics that the memory value, synaptic weights, can be increased or decreased incrementally. A novel SONOS synapse is used to read out the stored analog value. For the purpose of synapse implementation using SONOS NVSM, this work has investigated multiplying characteristics including weight updating characteristics and neuron output characteristics. It is concluded that SONOS synapse cell has good agreement for use as a synapse in artificial neural networks.

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An Integrated Approach of CNT Front-end Amplifier towards Spikes Monitoring for Neuro-prosthetic Diagnosis

  • Kumar, Sandeep;Kim, Byeong-Soo;Song, Hanjung
    • BioChip Journal
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    • v.12 no.4
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    • pp.332-339
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    • 2018
  • The future neuro-prosthetic devices would be required spikes data monitoring through sub-nanoscale transistors that enables to neuroscientists and clinicals for scalable, wireless and implantable applications. This research investigates the spikes monitoring through integrated CNT front-end amplifier for neuro-prosthetic diagnosis. The proposed carbon nanotube-based architecture consists of front-end amplifier (FEA), integrate fire neuron and pseudo resistor technique that observed high electrical performance through neural activity. A pseudo resistor technique ensures large input impedance for integrated FEA by compensating the input leakage current. While carbon nanotube based FEA provides low-voltage operation with directly impacts on the power consumption and also give detector size that demonstrates fidelity of the neural signals. The observed neural activity shows amplitude of spiking in terms of action potential up to $80{\mu}V$ while local field potentials up to 40 mV by using proposed architecture. This fully integrated architecture is implemented in Analog cadence virtuoso using design kit of CNT process. The fabricated chip consumes less power consumption of $2{\mu}W$ under the supply voltage of 0.7 V. The experimental and simulated results of the integrated FEA achieves $60G{\Omega}$ of input impedance and input referred noise of $8.5nv/{\sqrt{Hz}}$ over the wide bandwidth. Moreover, measured gain of the amplifier achieves 75 dB midband from range of 1 KHz to 35 KHz. The proposed research provides refreshing neural recording data through nanotube integrated circuit and which could be beneficial for the next generation neuroscientists.

Design of a Capacitive Detection Circuit using MUX and DLC based on a vMOS (vMOS 기반의 DLC와 MUX를 이용한 용량성 감지회로)

  • Jung, Seung-Min
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.11 no.4
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    • pp.63-69
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    • 2012
  • This paper describes novel scheme of a gray scale capacitive fingerprint image for high-accuracy capacitive sensor chip. The typical gray scale image scheme used a DAC of big size layout or charge-pump circuit of non-volatile memory with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit of charge sharing scheme is proposed, which uses DLC(down literal circuit) based on a neuron MOS(vMOS) and analog simple multiplexor. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, a pixel layout size can be reduced and the image resolution can be improved.

Narrative Review of the Association between Cervical Region Treatment and Facial Paralysis

  • Young-Jun Kim;Hye-Ri Jo;So-Rim Kim;Dong-Guk Shin;Da-Won Lee;Yeon-Sun Lee
    • Journal of Acupuncture Research
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    • v.40 no.4
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    • pp.319-328
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    • 2023
  • Facial nerve palsy refers to sudden, unilateral lower motor neuron facial paralysis. This study aimed to determine the importance of neck treatment in the treatment of facial paralysis. A literature search was performed on six online databases and other sources until January 15, 2023. A total of 426 papers were retrieved. After excluding duplicated and inconsistent papers, papers not including cervical treatment, and experimental papers on animals, two papers were finally selected. The type of treatment method, therapeutic effects, assessment of the risk of bias in randomized controlled trials, and non-randomized controlled trials and side effects were evaluated. Chiropractic, manual therapy, facial meridian massage, and acupotomy were applied to the face and cervical spine region. The results showed that each treatment had a significant therapeutic effect through evaluation index measurement methods, such as the visual analog scale and Yanagihara's unweighted regional grading system. This study demonstrated the importance of the cervical spine area in the treatment of facial paralysis. However, this study has many limitations. Thus, high-quality randomized controlled comparative studies on the treatment of the cervical spine area only or studies that include cervical spine area treatment as an interventional treatment while performing oriental or comprehensive treatment are needed.