• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Journal of Sensor Science and Technology
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• v.23 no.5
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• pp.332-336
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• 2014

In this paper, we propose a complementary metal oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) PMOSFET-type photodetector for high-speed operation. The GBT photodetector of an active pixel sensor (APS) consists of a floating gate ($n^+$-polysilicon) tied to the body (n-well) of the PMOSFET. The p-n junction photodiode that is used in a conventional APS has a good dynamic range but low photosensitivity. On the other hand, a high-gain GBT photodetector has a high level of photosensitivity but a narrow dynamic range. In addition, the pixel size of the GBT photodetector APS is less than that of the conventional photodiode APS because of its use of a PMOSFET-type photodetector, enabling increased image resolution. A CMOS binary image sensor can be designed with simple circuits, as a complex analog to digital converter (ADC) is not required for binary processing. Because of this feature, the binary image sensor has low power consumption and high speed, with the ability to switch back and forth between a binary mode and an analog mode. The proposed CMOS binary image sensor was simulated and designed using a standard CMOS $0.18{\mu}m$ process.

• Journal of Biomedical Engineering Research
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• v.35 no.6
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• pp.203-210
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• 2014

Wearable medical device has been a resurgence of interest thanks to the development of technology and propagation of smart phone in recent years. Various types of wearable devices have been introduced and available in market. Capacitive coupled electrode which measures electrocardiogram over cloth is able to be applied wearable device. In previous approaches of capacitive electrode, they need proper pressure for stable contact of the electrode to body surface. However, wearable device that gives pressure on body surface is not suitable for long-term monitoring. In this study, we proposed adhesive polyurethane-based capacitive electrode for patch-type wearable electrocardiogram (ECG) monitoring device. Self-adhesive polyurethane make the electrode and whole system be adhered to the surface of skin without any pressure. The patch-type system is consisted of analog filter, analog-to-digital converter and wireless transmission module and designed to be attached on the body as a patch. To validate the feasibility of the developed system, we measured ECG signal in stable and active state and extracted heart rate. Therefore, we observed skin response after long-term attachment for biocompatibility of the adhesive polyurethane and adhesive strength of it. The result shows the possibility of applying the developed system for ECG monitoring in real-life.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.5
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• pp.209-213
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• 2010

This paper is a study of Car safety network system using sensed data from varied sensors. This hardware will work with various sensors and communication protocols. There are many sensors. Then, I selected 3 sensors for test, which were sonic sensor for distance checking, tilt sensor for rollover and impact sensor for car accident and theft. Also, there are many interfaces for sensor. Therefore I designed hardware to support various sensor interfaces. For instance ADC(Analog to Digital converter), I2C, RS232, RS485, CAN. In this case, sonic sensor have I2C interface, tilt sensor have RS485 interface and Impact sensor have analog interface. In this research, I can gather sensing data from 3 sensors (mentioned above), and sending control signal to other processor with RS232, RS485, CAN communication. So, we can use easily this hardware for many cases of systems, which need sensors.

• Transactions of the Korean Society of Mechanical Engineers
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• v.8 no.2
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• pp.154-161
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• 1984

A modified technique of the transient hot wire method to measure the thermal conductivity of fluid has been described in this paper. The thermal conductivity of fluid can be obtained by acquiring wire temperature as a function of time. Multiplication of the inverse slope of the temperature versus logarithm of time by an instrumental constant gives the thermal conductivity. The constant voltage was applied to Wheatstone bridge circuit. The wire temperature can be measured as a function of time precisely with the aid of the data acquisition system composed of a microprocessor and an analog-digital converter. The thermal conductivity of the electrically conducting fluid has been measured with the insulated hot wire coated by electrically non-conducting material. The effect of the coated insulation layer on the thermal conductivity has been examined, in which it is confirmed that the thermal conductivity of electrically conducting liquid can be determined by the transient coated hot wire method. Thermal conductivities of methanol, carbontetrachrolide, Freon-22 and glycerin have been measured at room temperature in the pressure from 0.1MPa to 35.1MPa. The experiment has been performed to compare the data from the bare and the coated wires, and the results are satisfactory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.760-770
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• 2016

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.13-20
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• 2008

This paper describes the design of low power 12bit Digital-to-Analog Converter(D/A Converter) using Pseudo-Segmentation method which shows the conversion rate of 80MHz and the power supply of 1.8V with 0.18um CMOS n-well 1-poly 6-metal process for advanced wireless communication system. Pseudo-segmentation method used in binary decoder consists of simple parallel buffer is employed for low power because of simpler configuration than that of thermometer decoder. Also, using deglitch circuit and swing reduced drivel reduces a switching noise. The measurement results of the proposed low power 12bit 80MHz CMOS D/A Converter shows SFDR is 66.01dBc at sampling frequency 80MHz, input frequency 1MHz and ENOB is 10.67bit. Integral nonlinearity(INL) / Differential nonlinearity(DNL) have been measured ${\pm}1.6LSB/{\pm}1.2LSB$. Glich energy is measured $49pV{\cdot}s$. Power dissipation is 46.8mW at 80MHz(Maximum sampling frequency) at a 1.8V power supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1272-1280
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• 2008

In this paper, we have proposed a phase noise model of fast frequency hopping synthesizer with DDS Driven PLL architecture. To accurately model the phase noise contribution of noise sources in frequency hopping synthesizer, they were investigated using model of digital divider for PLL, DAC for DDS and Leeson's model for reference oscillator and VCO. Especially it was proposed that the noise component of low pass filter was considered together with the phase noise of VCO. Under assuming linear operation of a phase locked loop, the phase noise transfer functions from noise sources to the output of synthesizer was analyzed by superposition theory. The proposed phase noise prediction model was evaluated and its results were compared with measured data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.897-900
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• 2007

This paper presents a study on the DSP controller and IGBT inverter driver design for the power-by-wire(PBW) system using BLDC servo motor. This BLDC servo motor system was realized with DSP(Digital Signal Processor) and IGBT inveter module. The PBW system needs speed control of servo motor for linear thrust action. This paper implements a servo controller with vector control and min-max PWM technique. As CPU of controller, TMS320F2812 DSP was adopted because it has PWM(Pulse Width Modulation) waveform generator, A/D(Analog to Digital) converter, SPI( Serial Peripheral Interface) port and many input/output port etc.