• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• 한국전기전자재료학회논문지
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• 제37권4호
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• pp.400-406
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• 2024

Next-generation wide-bandgap semiconductors such as SiC, GaN, and Ga2O3 are being considered as potential replacements for current silicon-based power devices due to their high mobility, larger size, and production of high-quality wafers at a moderate cost. In this study, we investigate the gradual modulation of chemical composition in multi-stacked metal oxide semiconductor thin films to enhance the performance and bias stability of thin-film transistors (TFTs). It demonstrates that adjusting the Ga ratio in the indium gallium oxide (IGO) semiconductor allows for precise control over the threshold voltage and enhances device stability. Moreover, employing multiple deposition techniques addresses the inherent limitations of solution-processed amorphous oxide semiconductor TFTs by mitigating porosity induced by solvent evaporation. It is anticipated that solution-processed indium gallium oxide (IGO) semiconductors, with a Ga ratio exceeding 50%, can be utilized in the production of oxide semiconductors with wide band gaps. These materials hold promise for power electronic applications necessitating high voltage and current capabilities.

• Transactions on Electrical and Electronic Materials
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• 제17권6호
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• pp.351-354
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• 2016

The mechanical properties of ITO films such as adhesion and internal stress are very important for the commercial application of solar cell devices. We report high quality pulsed DC magnetron sputtered ITO films deposited on silicon and glass substrates with low resistivity and high transmittance for various working pressures ranging from 0.96 to 3.0 mTorr. ITO films showed the lowest resistivity of $2.68{\times}10^{-4}{\Omega}{\cdot}cm$, high hall mobility of $46.89cm^2/V.s$, and high transmittance (>85%) for the ITO films deposited at a low working pressure of 0.99 mTorr. The ITO films deposited at a low working (0.96 mTorr) pressure had both amorphous and polycrystalline structures and were found to have compressive stress while the ITO films deposited at higher temperature than 0.99 mTorr was mixture of amorphous and polycrystalline and was found to have tensile stress.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.151-151
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• 2010

In this paper, the electrically properties of nonvolatile memory (NVM) using multi-stacks gate insulators of oxide-nitride-oxynitride (ONOn) and active layer of the low temperature polycrystalline silicon (LTPS) were investigated. From hydrogenated amorphous silicon (a-Si:H), the LTPS thin films with high crystalline fraction of 96% and low surface's roughness of 1.28 nm were fabricated by the metal induced crystallization (MIC) with annealing conditions of $650^{\circ}C$ for 5 hours on glass substrates. The LTPS thin film transistor (TFT) or the NVM obtains a field effect mobility of ($\mu_{FE}$) $10\;cm^2/V{\cdot}s$, threshold voltage ($V_{TH}$) of -3.5V. The results demonstrated that the NVM has a memory window of 1.6 V with a programming and erasing (P/E) voltage of -14 V and 14 V in 1 ms. Moreover, retention properties of the memory was determined exceed 80% after 10 years. Therefore, the LTPS fabricated by the MIC became a potential material for NVM application which employed for the system integration of the panel display.

• 대한금속재료학회지
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• 제50권8호
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• pp.575-582
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• 2012

Medium carbon steel was aluminized by hot dipping into molten Al or Al-1 at% Si baths. After hot-dipping in these baths, a thin Al-rich topcoat and a thick alloy layer rich in $Al_5Fe_2$ formed on the surface. A small amount of FeAl and $Al_3Fe$ was incorporated in the alloy layer. Silicon from the Al-1 at% Si bath was uniformly distributed throughout the entire coating. The hot dipping increased the microhardness of the steel by about 8 times. Heating at $700-1000^{\circ}C$, however, decreased the microhardness through interdiffusion between the coating and the substrate. The oxidation at $700-1000^{\circ}C$ in air formed a thin protective ${\alpha}-Al_2O_3$ layer, which provided good oxidation resistance. Silicon was oxidized to amorphous silica, exhibiting a glassy oxide surface.

• 한국지구과학회지
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• 제22권3호
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• pp.208-222
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• 2001

이 연구는 전남 광양광산과 그 주변의 하천에 형성되어 있는 부유성 비정질 퇴적물의 지구화학적 특성을 밝히기 위해 수행되었다. 부유성 비정질 퇴적물의 주요성분은 Fe$_2$O$_3$이며, Fe$_2$O$_3$의 함량은 17.9${\cdot}$72.3wt.% 범위로 나타난다. Fe함량이 증가하면 Si, Al, Mg, Na, K, Mn 및 Ti 함량이 감소하며 Te, Au, Ga, Bi, Cd, Hg, Sb, 및 Se등의 함량은 증가한다. 하상 침전물인 비정질 퇴적물에는 As(최대 54.9ppm), Bi(최대 3.77ppm), Cd(최대 3.65ppm), Hg(최대64ppm), Sb(최대 10.1ppm), Cu (최대 37.1ppm), Mo(최대 8.86ppm), Pb(최대 9.45ppm) 및 Zn(최대 29.7ppm) 등의 중금속원소가 농집되어 있다. 황갈색 침전물에는 Au(최대 4.40ppm)와 Ag(최대 0.24ppm) 함량이 매우 높게 나타나며, Au함량은 하천의 상류지역에 높은 함량을 보이다가 하류지역으로 갈수록 그 함량이 감소한다. 반면에 Ag 함량은 상류지역의 하천에 낮은 함량을 보이다가 하류지역으로 갈수록 그 함량이 증가하여 나타난다. XRD분석에서 하상의 황갈색 침전물은 X-선회절선이 뚜렷하지 않은 비정질이거나 결정도가 미약한 철수산화물로 밝혀졌으며, 석영, 침철석, 고령토, 일라이트 등이 관찰된다. IR분석에서 비정질 하상 퇴적물은 OH기, H$_2$O, SO$_4$ 및 Fe-O 기에 의한 흡수밴드가 관찰된다.

• Journal of Electrical Engineering and Technology
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• 제6권2호
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• pp.270-274
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• 2011

This paper presents a parameterized simulation program with integrated circuit emphasis (SPICE) model of a two-level microbolometer based on negative-temperature-coefficient thin films, such as vanadium oxide or amorphous silicon. The proposed modeling begins from the electric-thermal analogy and is realized on the SPICE modeling environment. The model consists of parametric components whose parameters are material properties and physical dimensions, and can be used for the fast design study, as well as for the co-design with the readout integrated circuit. The developed model was verified by comparing the obtained results with those from finite element method simulations for three design cases. The thermal conductance and the thermal capacity, key performance parameters of a microbolometer, showed the average difference of only 4.77% and 8.65%, respectively.

• 전자공학회논문지A
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• 제30A권8호
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• pp.34-41
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• 1993

Effect of high temperature annealing conditions on Ta$_{2}O_{5}$ thin films was investigated. Ta$_{2}O_{5}$ thin films were deposited on P-type silicon substrates by plasma-enhanced chemical vapor deposition (PECVD) using tantalum ethylate. Ta(C$_{2}H_{5}O)_{5}$, and nitrous oxide. N$_{2}$O. The microstructure changed from amorphous to polycrystalline above 700.deg. C annealing temperature. The refractive index, dielectric onstant and leakage current of the film increased as annealing temperature increased. However, annealing in oxygen ambient reduced leakage currents and dielectric constant due to the formation of interfacial SiO$_{2}$ layer. By optimizing annealing temperature and ambient, leakage current lower than 10$^{-8}$ A/cm$^{2}$ and maximum capacitance of 9 fF/${\mu}m^{2}$ could be obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.695-698
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• 2006

The photosensitive poly-siloxane material used as the passivation layers for the conventional back channel etched (BCE) thin film transistors (TFTs) has been investigated. Through the organic material, the TFT array fabrication process can be reduced and higher aperture ratio can be achieved for higher LCD panel performance. The interface between the organic passivation layer and the back channel of the amorphous active region has been improved by the back channel oxygen treatment and the devices exhibits lower leakage current than the conventional silicon nitride passivation layer of BCE TFTs. The leakage currents between Indium-tin-oxide (ITO) pixels and the TFT devices and its mechanism have also been investigated in this paper.