• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.567-571
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• 2009

Polycrystalline ZnO and Ga doped ZnO (GZO) films are deposited on glass substrate by RF magnetron sputtering at room temperature. The characteristics of ZnO and GZO films are investigated with X-ray diffraction measurement, UV-VIS-NIR spectrophotometer $(250{\sim}1200nm)$ and hall measurement. The post-growth thermal treatment of these films is carried out in N2 ambient at $500^{\circ}C$ for 30 min and an hour. ZnO and GZO films have different changing behavior of structural and optical properties by annealing. To use transparent conductive films for solar cell, films should have not only high transmittance but also good electrical property. Although as deposited GZO films have electrical properties than ZnO films, GZO films have not good transmittance properties. Consequently, we succeed that the high transmittance of GZO films is improved by annealing process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.5
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• pp.441-448
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• 2002

The electrical properties of the GaN-based green light emitting diodes(LEDs) with the Mg-doped p-GaN layer activated in $N_2$ or $O_2$ ambient have been compared. For the $N_2$ -ambient activation the current-voltage behavior of LEDs has been found to be improved when the Mg dopants activation was performed in the higher temperature. However, for the $O_2$-ambient activation the current-voltage characteristic has been observed to be enhanced when the Mg dopants activation was carried out in the lower temperature. The minimum forward voltage at 20mA was obtained to be 4.8 V for LEDs with the p-GaN layer activated at $900^{\circ}C$ in the $N_2$ ambient and 4.5V for LEDs with the p-GaN layer treated at $700^{\circ}C$ in the $O_2$ambient, repectively. The forward voltage reduction of the LEDs treated in the $O_2$-ambient may be related to the oxygen co-doping of the p-GaN layer during the activation process. The $O_2$ -ambient activation process is useful for the enhancement of the LED performance as well as the fabrication process since this process can activate the Mg dopants in the low temperature.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.417-418
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• 2008

Transparent conductive oxide (TCO) are necessary as front electrode or anti-reflecting coating for increasing efficiency of LED and Photodiode. In this paper, aluminum-doped Zinc oxide films(AZO) were prepared by DC magnetron sputtering on glass(corning 1737) and Si substrate at temperature of $100^{\circ}C$ and then annealed at temperature of $400^{\circ}C$ for 1hr in Ar and vaccum. The AZO films were etched in diluted HCL (0.5 %) to examine the surface morphology properties. After annealing, Structural and electrical property were investigated. The c-axis orientation along (002) plane was enhanced and the electrical resistivity of the AZO film decreased from $1.1\times10^{-1}$ to $1.6\times10^{-2}{\Omega}cm$. We observed textured structure of AZO thin film etched for 2s.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03b
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• pp.17-17
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• 2010

Polycrystalline $CuInS_2$ thin films were performed from S/In/Cu Stacked elemental layer(SEL) method with post annealing. In thin method, the thin films were annealed in Vacuum of $10^{-3}$ torr or in S ambient. $CuInS_2$ thin films were manufctured by using the evaporation and the annealing with vacuum quartz furnace of sulfurization process was used in the vacuum chamber to the substrate temperature on the glass substrate the annealing temperature and characteristics thereof were investigated. The physical properties of the thin film were investigated under various fabrication conditions including the substrate temperature annealing time by XRD, FE-SEM, and Hall measurement system.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.4
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• pp.29-33
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• 2003

Material and electrical properties of copper-based ohmic contacts on n-type 4H-SiC were investigated for the effects of the post-annealing and the metal covering conditions. The ohmic contacts were prepared by sequential sputtering of Cu and Si layers on SiC substrate. The post-annealing treatment was performed using RTP (rapid thermal process) in vacuum and reduction ambient. The specific contact resistivity ($p_{c}$), sheet resistance ($R_{s}$), contact resistance ($R_{c}$), transfer length ($L_{T}$), were calculated from resistance (RT) versus contact spacing (d) measurements obtained from TLM (transmission line method) structure. The best result of the specific contact resistivity was obtained for the sample annealed in the reduction ambient as $p_{c}= 1.0 \times 10^{-6}\Omega \textrm{cm}^2$. The material properties of the copper contacts were also examined by using XRD. The results showed that copper silicide was formed on SiC as a result of intermixing Cu and Si layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.127.1-127.1
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• 2011

In this paper, ZnO:Al thin films with c-axis preferred orientation were prepared on Soda lime glass substrates by RF magnetron sputtering technique. AZO thin film were prepared in order to clarify optimum conditions for growth of the thin film depending upon process, and then by changing a number of deposition conditions and substrate temperature conditions variously, structural and electrical characteristics were measured. For the manufacture of the AZO were vapor-deposited in the named order. It is well-known that post-annealing is an important method to improve crystal quality. For the annealing process, the dislocation nd other defects arise in the material and adsorption/decomposition occurs. The XRD patterns of the AZO films deposited with grey theory prediction design, annealed in a vacuum ambient($2.0{\times}10-3$Torr)at temperatures of 200, 300, 400 and $500^{\circ}C$ for a period of 30min. The diffraction patterns of all the films show the AZO films had a hexagonal wurtzite structure with a preferential orientation along the c-axis perpendicular to the substrate surface. As can be seen, the (002)peak intensities of the AZO films became more intense and sharper when the annealing temperature increased. On the other hand, When the annealing temperature was $500^{\circ}C$ the peak intensity decreased. The surface morphologies and surface toughness of films were examined by atomic force microscopy(AFM, XE-100, PSIA). Electrical resistivity, Gall mobility and carrier concentration were measured by Hall effect measuring system (HL5500PC, Accent optical Technology, USA). The optical absorption spectra of films in the ultraviolet-visibleinfrared( UV-Vis-IR) region were recorder by the UV spectrophotometer(U-3501, Hitachi, Japan). The resistivity, carrier concentration, and Hall mobility of ZnS deposited on glass substrate as a function of post-annealing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.180-184
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• 2002

In this paper, the electrical properties of PVD Ta and $TaN_x$ gate electrodes on $SiO_2$ and their thermal stabilities are investigated. The results show that the work functions of $TaN_x$ gate electrode are modified by the amount of N, which is controlled by the flow rate of $N_2$during reactive sputtering process. The thermal stability of Ta and $TaN_x$ with RTO-grown $SiO_2$ gate dielectrics is examined by changes in equivalent oxide thickness (EOT), flat-band voltage ($V_{FB}$), and leakage current after post-metallization anneal at high temperature in $N_2$ambient. For a Ta gate electrode, the observed decrease in EOT and leakage current is due to the formation of a Ta-incorporated high-K layer during the high temperature annealing. Less change in EOT and leakage current is observed for $TaN_x$ gate electrode. It is also shown that the frequency dispersion and hysteresis of high frequency CV curves are improved significantly by a post-metallization anneal.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.