• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권5호
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• pp.319-325
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• 1999

Direct current(d.c.)leakage current voltage characteristics of radio-frequencymagnetron sputtered BaTa\sub 2\O\sub 6\ film capacitors with aluminum(A1) top and indium tin oxide (ITO) bottom electrodes have been investigatedas a function of applied field and temperature. In order to study surfacetreatment effect on the electrical characteristics of as-deposited film weperformed exposure of oxygen plasma on $BaTa_2O_6$ surface. d. c.current-voltage (I-V), bipolar pulse charge-voltage (Q-V), d. c. current-time (I-t) andcapacitance-frequency (C-f) analysis were performed on films. All ofthe films exhibita low leakage current, a high breakdown field strength (3MV/cm-4.5MV/cm), and high dielectric constant (20-30). From the temperature dependence of leakage current,we can conclude that the dominant conduction mechanism is ascribed toSchottky emission at high electric field (>1MV/cm) and hopping conduction at lowelectric field (<1MV/cm). According to our results, the oxide plasma surfacetreatmenton as-deposited $BaTa_2O_6$ resulted in lowering interfacebarrier height and thus, leakage current when a negative voltage applied to the A1 electrode. This can be explained by reduction of surface contamination via etching surface and filling defects such as oxygen vacancies.

• Restorative Dentistry and Endodontics
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• 제41권2호
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• pp.106-113
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• 2016

Objectives: This study evaluated the effects of different surface conditioning methods on the bond strength of orthodontic brackets to glazed full-zirconia surfaces. Materials and Methods: Glazed zirconia (except for the control, Zirkonzahn Prettau) disc surfaces were pre-treated: PO (control), polishing; BR, bur roughening; PP, cleaning with a prophy cup and pumice; HF, hydrofluoric acid etching; AA, air abrasion with aluminum oxide; CJ, CoJet-Sand. The surfaces were examined using profilometry, scanning electron microscopy, and electron dispersive spectroscopy. A zirconia primer (Z-Prime Plus, Z) or a silane primer (Monobond-S, S) was then applied to the surfaces, yielding 7 groups (PO-Z, BR-Z, PP-S, HF-S, AA-S, AA-Z, and CJ-S). Metal bracket-bonded specimens were stored in water for 24 hr at $37^{\circ}C$, and thermocycled for 1,000 cycles. Their bond strengths were measured using the wire loop method (n = 10). Results: Except for BR, the surface pre-treatments failed to expose the zirconia substructure. A significant difference in bond strengths was found between AA-Z ($4.60{\pm}1.08MPa$) and all other groups ($13.38{\pm}2.57-15.78{\pm}2.39MPa$, p < 0.05). For AA-Z, most of the adhesive remained on the bracket. Conclusions: For bracket bonding to glazed zirconia, a simple application of silane to the cleaned surface is recommended. A zirconia primer should be used only when the zirconia substructure is definitely exposed.

• 한국재료학회지
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• 제16권12호
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• pp.731-738
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• 2006

It is seriously considered using Al CMP (chemical mechanical planarization) process for the next generation 45 nm Al wiring process. Al CMP is known that it has a possibility of reducing process time and steps comparing with conventional RIE (reactive ion etching) method. Also, it is more cost effective than Cu CMP and better electrical conductivity than W via process. In this study, we investigated 4 different kinds of slurries based on abrasives for reducing scratches which contributed to make defects in Al CMP. The abrasives used in this experiment were alumina, fumed silica, alkaline colloidal silica, and acidic colloidal silica. Al CMP process was conducted as functions of abrasive contents, $H_3PO_4$ contents and pressures to find out the optimized parameters and conditions. Al removal rates were slowed over 2 wt% of slurry contents in all types of slurries. The removal rates of alumina and fumed silica slurries were increased by phosphoric acid but acidic colloidal slurry was slightly increased at 2 vol% and soon decreased. The excessive addition of phosphoric acid affected the particle size distributions and increased scratches. Polishing pressure increased not only the removal rate but also the surface scratches. Acidic colloidal silica slurry showed the highest removal rate and the lowest roughness values among the 4 different slurry types.

• 한국포장학회지
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• 제29권3호
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• pp.223-228
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• 2023

Sustainable energy supplies without the recharging and replacement of the charge storage device have become increasingly important. Among various energy harvesters, the triboelectric nanogenerator (TENG) has attracted considerable attention due to its high instantaneous output power, broad selection of available materials, eco-friendly and inexpensive fabrication process, and various working modes customized for target applications. In this study, the amount of voltage and current generated was measured by applying the PSD profile random vibration test of the electronic vibration tester and ISTA 3A according to the time of Anodized Aluminum Oxide (AAO) pore widening of the manufactured TENG device Teflon and AAO. The discharge and charging tests of the integrated module during the random simulated transport environment and the recognition distance of RFID were measured while agricultural products (onion) were loaded into the returnable folding plastic box. As a result, it was found that AAO alumina etching processing time to maximize TENG performance was optimal at 31 min in terms of voltage and current generation, and the integrated module applied with the TENG module showed a charging effect even during the continuous use of RFID, so the voltage was kept constant without discharge. In addition, the RFID recognition distance of the integrated module was measured as a maximum of 1.4 m. Therefore, it was found that the surface condition of AAO, a TENG element, has a great influence on the power generation of the integrated module, and due to the characteristics of TENG, the power generation increases as the surface dries, so it is judged that the power generation can be increased if the surface drying treatment (ozone treatment, etc.) of AAO is applied in the future.

• 공업화학
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• 제25권5호
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• pp.447-454
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• 2014

유기태양전지는 제조비용이 저렴하고 플렉서블 전자소자에 적용이 가능하다는 장점들로 인해 최근 많은 연구가 진행되고 있다. 일반적인 정구조의 태양전지(conventional structured solar cell)의 경우 10%대의 향상된 발전 효율을 보이고 있으나, 여전히 기타 Si 및 CIGS 등과 같은 태양전지에 비해 낮은 효율과 짧은 수명은 상용화의 걸림돌로 작용하고 있다. 일반적으로 유기태양전지의 짧은 수명은 유기물의 광산화뿐만 아니라 수분 및 산소에 의한 음극, 양극 소재의 부식으로 인한 소재/소자 열화 문제로 설명되어지고 있다. 한편 이와 같은 문제점을 해결하기 위해 새로운 소자 구조(역구조 태양 전지; Inverted structured solar cell)가 제안되었으며 전자 수송층 및 기능성 계면 소재 연구를 통한 발전 효율 및 수명 향상에 관한 연구가 꾸준히 되고 있다. 그 결과 최근 2D/3D 산화 아연(ZnO) 소재를 역구조 태양전지의 전자 수송층으로 적용하고 건,습식 표면 후처리를 통해 약 9% 수준의 발전효율을 달성하였다. 본 총설에서는 ZnO를 기반으로 하는 전자 수송층 소재의 연구 동향 및 역구조 태양전지의 효율 향상 기술에 관한 최신 연구 동향을 소개하고자 한다.

• 대한기계학회논문집A
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• 제36권10호
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• pp.1189-1193
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• 2012

본 연구는 초소형 광학 시스템을 구현할 수 있는 설계 및 제작의 방법론을 제시하고자 한다. 초소형 광학계에서는 조명 및 결상 광학소자의 성능과 소형화가 조광면의 균질도와 결상 된 이미지의 선명도에 중요한 영향을 미치게 된다. 본 연구에서는 얇은 두께로 실효 광도를 배가시키기 위한 초박형의 LED 빔조형 렌즈를 설계 제작하였다. 상기 렌즈는 중앙부의 비구면렌즈와 외각의 전반사 프레넬 가장자리 부로 구성되어 있다. 설계된 LED 빔조형 렌즈(직경 4.7 mm, 두께 0.6 mm)는 다이아몬드 선삭으로 중앙 비구면부의 전반사(TIR) 가장자리가 정밀하게 가공되었으며, LED 의 빔각을 150 도에서 17.5 도로 축소 시켰다. 다른 광학소자들 마이크로 프리즘, 결상광학용 프레넬 렌즈, 광가이드는 다양한 마이크로 나노 크기의 제조공정으로 일체형으로 성형되었다. 시작품으로 제작된 초소형 광학계($6.8{\times}2.2{\times}2.5mm$)는 마이크로 패턴을 결상의 가능성을 보여주었고, 지문인식용 초소형광학계로서의 성능을 검증하였다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Composites Research
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• 제13권4호
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• pp.42-53
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• 2000

차세대 항공기소재로 관심을 가지고 있는 Al 7075/CFRP 적층 복합재인 CARALL(CARbon ALuminum Laminates)하이브리드 복합소재 제조를 위한 중요조건중의 하나인 Al 표면처리조건과 경화방법에 대해 조사하였다. 항공기용 Al 전처리 중 대표적인 것으로 증기탈지, 크롬산 양극산화 피막처리, 황산-중크롬산 나트륨 에칭처리 및 인산 양극산화 피막처리공정이 있다. 본 실험에서는 상기 전처리 공정을 모두 항공 규격에 준해서 실시하여 Lap shear 및 Bell peel strength를 비교함으로써 효과적인 접착강도를 나타내는 표면처리 공정을 찾아내고, 시편의 자연표면상태를 그대로 관찰할 수 있는 AFM(Atomic Force Microscope)장비를 이용하여 각 전처리 시편의 표면형상을 측정함으로써 표면형상과 접착강도와의 상관관계를 고찰 하였다. 그리고 Al 표면처리와 별도로 Al과 접착제 및 탄소섬유 프리프레그를 동시에 경화시키는 방법과 탄소섬유 프리프레그를 미리 경화시킨후 다시 Al과 탄소섬유 라미네이트를 접착필름을 이용하여 재 접착시키는 이차 경화법을 적용하여 상호 접착강도 및 물성을 비교하였다. 또한 이차경화법에서의 오토클레이브 압력 변화와 DMA(Dynamic Mechanical Analysis) 장비를 이용한 접착필름의 유리전이온도($T_g$) 측정을 통해 효과적인 공정압력 및 접착내구성 유지에 필요한 최소 경화시간을 파악하였다. 상기 결과로부터 정밀 치수관리가 필요하며 고접착강도, 내구성 항공기 부품을 제작하기 위한 알루미늄 표면처리 공정과 복합재 경화공정 조건을 제시하고자 하였다.

• Corrosion Science and Technology
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• 제9권6호
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• pp.276-280
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• 2010

Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.