• 한국생물정보학회:학술대회논문집
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• 한국생물정보시스템생물학회 2004년도 The 3rd Annual Conference for The Korean Society for Bioinformatics Association of Asian Societies for Bioinformatics 2004 Symposium
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• pp.77-85
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• 2004

A significant portion (about 8% in human genome) of mammalian mRNA sequences contains AU(Adenine and Uracil) rich elements or AREs at their 3' untranslated regions (UTR). These mRNA sequences are usually stable. ARE motifs are assorted into three classes. The importance of AREs in biology is that they make certain mRNA unstable. We analyzed the occurrences of AREs and Alu, and propose a possible mechanism on how human mRNA could acquire and keep A REs at its 3' UTR originated from Alu repeats. Interspersed in the human genome, Alu repeats occupy 5% of the 3' UTR of mRNA sequences. Alu has poly-adenine (poly-A) regions at the end that lead to poly -thymine (poly-T) regions at the end of its complementary Alu. It has been discovered that AREs are present at the poly -T regions. In the all ARE's classes, 27-40% of ARE repeats were found in the poly -T region of Alu with mismatch allowed within 10% of ARE's length from the 3' UTRs of the NCBI's reference m RNA sequence database. We report that Alu, which has been reported as a junk DNA element, is a source of AREs. We found that one third of AREs were derived from the poly -T regions of the complementary Alu.

• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 춘계학술대회
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• pp.229-232
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• 2009

최근 모바일 기기에서도 고성능 그래픽 효과가 요구되면서 다양한 연산 처리를 하는 프로그래머블 쉐이더가 필요하게 되었다. 이러한 이유로 프로그래머블 쉐이더 프로세서의 ALU는 기존에 비해 상대적으로 커지게 되었다. 이 논문에서 제안하는 듀얼 페이지 구조는 프로그래머블 쉐이더에서 상대적으로 커진 ALU 하나를 이용하여 동시에 두 개의 연산 처리를 가능하게 하는 구조이다. 이러한 구조를 사용하여 기존 구조에 비해 평균 40%의 성능을 개선 하였다.

• Progress in Superconductivity
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• 제5권1호
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• 전자공학회논문지B
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• 제28B권7호
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1169-1172
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• 1998

We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.

• 한국미생물·생명공학회지
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• 제49권3호
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• pp.316-319
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• 2021

Restriction endonucleases play an important role in molecular cloning, clinical diagnosis, and pharmacological drug studies. In this study, DNA-templated copper nanoclusters (DNA-CuNCs) were used to detect AluI endonuclease activity due to their high fluorescence emission and rapid synthesis of DNA-CuNCs under ambient conditions. Results showed that AluI activity was detected in a highly sensitive manner at low concentrations of AluI endonuclease by the fluorescence intensity of DNA-CuNCs. Additionally, its inhibition was monitored in the presence of daidzein under optimal conditions.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.59-65
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• 2013

저전력 설계를 요구하는 디지털 시스템에서는 동적 전력(dynamic power)과 누설 전력(leakage power) 사이의 균형을 이루는 점에 근접하는 매우 낮은 전압에서 작동하는 디지털 설계 방식을 요구하지만, 기존의 동기방식의 회로는 낮은 전압에서 지연(delay)이 급격히 증가하여 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라, 공정, 전압, 온도 변이 (PVT variation) 등에 크게 영향을 받아서 올바른 동작을 기대할 수 없다. 따라서 본 논문에서는 낮은 전압에서 여러 가지 변이들에 영향을 받지 않는 비동기회로 설계 방식 중에 타이밍 분석이 요구되지 않고, 설계가 간단한 NCL (Null Convention Logic) 방식을 사용한 저전력 산술논리 연산장치 (ALU) 회로를 매그나칩-SK하이닉스 0.18um 공정으로 설계하고, 기존의 파이프라인 방식의 ALU와 스피드와 전력에 관해서 비교하였다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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• pp.123.2-123.2
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• 2011

$ALU^+$ 태양전지는 PN접합을 후면에서 즉, Al을 소성하여 형성시키기 때문에 얼마나 균일하고 두껍게 형성하는 것이 가장 중요하다. 소성(Firing)은 태양전지 제조 과정에서 후면의 접촉을 위한 중요한 공정이다. 본 연구에서는 상업화가 가능한 n-type $ALU^+$ Emitter 태양전지에서 소성 횟수에 따른 특성을 연구 하였다. $ALU^+$ emitter 형성의 최적화를 위해 소성온도를 가변하고, 최적화된 온도에서 소성 횟수에 따른 DIV 측정을 통해 셀을 분석 하였다. 소성 횟수는 1~3회로 하였고, 그 결과 단락전류 밀도(Jsc)가 33.57mA/$cm^2$로 처음보다 15.1%증가 하였고, 곡선인자(Fill Factor)는 3회에서 66.04%로 218%증가 하였다. Al을 짧은 시간 안에 소성을 시키므로 해서 후면의 $P^+$ Emitter가 균일하게 형성되었기 때문에 개방전압(Voc)의 증가를 확인하였다. 본 연구를 통해 $ALU^+$ 태양전지의 후면 Aluminium 소성 조건의 최적화를 통하여 $ALU^+$ emitter가 충분히 형성되지 못하면 누설전류가 발생되고 직렬저항(Rs)이 크게 증가하여 개방전압(Voc) 및 단락전류밀도(Jsc)의 감소가 발생하게 되고, 직렬저항(Rs)의 증가와 병렬저항(Rsh)의 감소는 Fill Factor의 급격한 감소를 초래하게 됨을 알 수 있다. 이를 개선하면 태양전지 효율을 상승시키는 결과를 얻을 수 있음을 확인하였다.

• Progress in Superconductivity
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• 제6권2호
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.