• 제목/요약/키워드: Alloy semiconductor

검색결과 90건 처리시간 0.027초

반도체용 박막재료의 열응력-변형 특성에 미치는 passivation 층의 영향 분석 (Effects of passivation layer on the thermal deformation behavior of metal film used in semiconductor devices)

  • 최호성;이광렬;권동일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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    • pp.732-734
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    • 1998
  • Metal thin films such as aluminum have been used as interconnects in semiconductor device. Recently, these materials are applied to structural materials in microsensors and microactuators. In this study, we evaluate deformation and strength behavior of aluminum alloy film. Three layer model for thermal deformation of multilayered thin film material is introduced and applied to Si/Al(1%Si)/$SiO_2$ system. Based on beam bending theory and concept of bending strain. elastic and elastic/plastic thermal deformation behaviors of multilayered materials can be estimated. In the case of plastic deformation of ductile layer, strain rate equations based on deformation mechanism map are employed for describe the stress relaxation effect. To experimentally examine deformation of multilayered thin film materials, in-situ laser scanning method is used to measure curvature of specimens during heating and cooling. The thickness of $SiO_2$ layer is varied to estimate third-layer effect of thermal deformation of metal films, and its effect on deformation behavior are discussed.

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탄소나노튜브 함유 Solderable 도전성 접착제의 전기적/기계적 접합특성 평가 (Electrical and Mechanical Properties of CNT-filled Solderable Electrically Conductive Adhesive)

  • 임병승;정진식;이정일;오승훈;김종민
    • 반도체디스플레이기술학회지
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    • 제10권4호
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    • pp.37-42
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    • 2011
  • In this paper, novel carbon nanotube (CNT)-filled Solderable electrically conductive adhesive (ECA) and joining process have been developed. To investigate the bonding characteristics of CNT-filled Solderable ECA, three types of Solderable ECAs with different CNT weight percent (0, 0.1, 1wt%) were formulated. For a joining process, the quad flat package (QFP) chip was used. The QFP chip had a size of $14{\times}14{\times}2.7$ mm and a 1 mm lead pitch. The test board had a Cu daisy-chained pattern with 18 ${\mu}m$ thick. After the bonding process, the bonding characteristics such as morphology of conduction path, electrical resistance and pull strength were measured for each formulated ECAs. As a result, the electrical and mechanical bonding characteristics for a QFP joints using CNT-filled ECA were improved about 10% compared to those of QFP joints using ECA without CNT.

LED 및 반도체 소자 리드프레임 패키징용 Cu/STS/Cu 클래드메탈의 기계적/열전도/전기적 특성연구 (Study on the Mechanical Properties and Thermal Conductive Properties of Cu/STS/Cu Clad Metal for LED/semiconductor Package Device Lead Frame)

  • 이창훈;김기출;김용성
    • Journal of Welding and Joining
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    • 제30권3호
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    • pp.32-37
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    • 2012
  • Lead frame which has a high thermal conductivity and high mechanical strength is one of core technology for ultra-thin electronics such as LED lead frames, memory devices of semiconductors, smart phone, PDA, tablet PC, notebook PC etc. In this paper, we fabricated a Cu/STS/Cu 3-layered clad metal for lead frame packaging materials and characterized the mechanical properties and thermal conductive properties of the clad metal lead frame material. The clad metal lead frame material has a comparable thermal conductivity to typical copper alloy lead frame materials and has a reinforced mechanical tensile strength by 1.6 times to typical pure copper lead frame materials. The thermal conductivity and mechanical tensile strength of the Cu/STS/Cu clad metal are 284.35 W/m K and $52.78kg/mm^2$, respectively.

SSD 테스터의 알루미늄 합금 Guide Hole의 마모에 관한 연구 (A Study on Wear of Aluminum Alloy Guide Hole in SSD Tester)

  • 함응진;김문기
    • 반도체디스플레이기술학회지
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    • 제21권2호
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    • pp.19-24
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    • 2022
  • The purpose of this research is to determine the hardness of guide hole. A guide pin and a guide hole of SSD(Solid State Drive) tester used to mount SSD in a fixed position accurately. The guide pin and guide hole are worn by friction due to repeated operation, and the wear is concentrated on the guide hole made of weak material rather than the guide pin made of relatively strong material. Because of that reason, it is often overdesigned in the design stage because it can lose its function. If the guide hole is made soft, the manufacturing cost will decrease, but the accuracy will decrease due to wear caused by repeated friction. If the guide hole is manufactured excessively, the manufacturing process becomes complicated and the manufacturing cost increases. It is essential to design a guide hole, but since there is no standard or verified data that can be referenced, it is difficult to design. Experimental device which guides in the same way as the SSD tester is used for this research, and three types of anodizing state are experimented for different hardness. Also, weight of COK(Change over Kit) were analyzed by measuring the wear amount and state of the guide hole according to the number of repeated attachment and detachment.

Fe/Ni 합금전착에 의한 다공성 그물군조 방열재료의 제조 연구 (Fabrication of Porous Reticular Metal by Electrodeposition of Fe/Ni Alloy for Heat Dissipation Materials)

  • 이화영;이관희;정원용
    • 전기화학회지
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    • 제5권3호
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    • pp.125-130
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    • 2002
  • 다공성 그물구조 금속을 반도체 칩 방열재료로써 활용하기 위한 실험을 실시하였다. 이를 위해 다공성 그물구조 구리와 반도체 칩 사이의 열팽창 차이를 최소화하기 위한 시도로써 다공성 구리에 대한 Fe/Ni 합금전착을 수행하였다. Fe/Ni 합금전착 실험으로 표준 Hull Cell을 구성하고 전류밀도 분포에 따른 Fe/Ni 합금층 내의 조성변화를 관찰하였으며, 실험결과 합금전착시 이상공석현상으로 인하여 전해액의 교반정도에 따라 합금층 조성이 크게 영향을 받는 것으로 나타났다. 본 실험에서는 paddle type 교반기를 사용하여 전해질의 확산을 제어하는 방법으로 원하는 조성의 Fe/Ni 합금층을 얻을 수 있었으며, 얻어진 Fe/Ni 후막을 대상으로 TMA 열분석을 실시한 결과 구리에 비해 훨씬 낮은 열팽창율을 보이는 것으로 나타났다. 또한, 본 실험에서 Fe/Ni 합금전착을 통하여 제작한 다공성 그물구조 금속을 대상으로 방열성능을 측정한 결과 구리 평판 대비 최대 2배 이상의 방열성능을 보여 반도체 칩 방열재료로의 활용 가능성을 높여 주었다.

솔더 합금 종류 및 솔더 조인트의 신뢰성 평가 기법 (Solder Alloy Types and Solder Joint Reliability Evaluation Techniques)

  • 김유권;김헌수;김태완;김학성
    • 마이크로전자및패키징학회지
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    • 제30권1호
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    • pp.17-29
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    • 2023
  • 본 논문에서는 전자제품의 소형화와 고성능화에 따라 패키징 기술에서 핵심적인 역할을 하는 솔더 조인트의 신뢰성 평가 방법을 소개한다. 우선, 다양한 합금 조성과 제품 형태에 따른 솔더의 특성을 설명하고, 여러 패키지에서의 솔더 조인트 구조에 대한 개요를 제시한다. 그 다음 솔더 합금의 조성과 미시구조가 솔더의 열적 및 기계적 특성에 미치는 영향을 분석하며, 솔더 크리프 거동에 대해 간략히 소개한다. 이어서, 신뢰성 평가를 위한 크리프 모델과 피로 모델 등을 고려한 분석 기법들을 소개하고, 솔더 조인트의 신뢰성을 향상시킬 수 있는 방안에 대해 논의한다. 본 연구는 반도체 패키징 기술 분야에서 솔더 조인트의 신뢰성 평가와 개선에 유익한 정보를 제공할 것으로 기대된다.

NiPt/Co/TiN을 이용한 Ni Germanosilicide 의 열안정성 향상 및 Ge 비율 (x) 에 따른 특성 분석 (Thermal Stability Improvement or Ni Germanosilicide Using NiPt/Co/TiN and the Effect of Ge Fraction (x) in $Si_{l-x}Ge_x$)

  • 윤장근;오순영;황빈봉;김용진;지희환;김용구;차한섭;허상범;이종근;왕진석;이희덕
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.391-394
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    • 2004
  • In this study, highly thermal stable Ni Germanosilicide has been utilized using NiPt alloy and novel NiPt/Co/TiN tri-layer. And, the Ni Germanosilicide Properties were characterized according to different Ge ratio (x) in $Si_{l-x}Ge_x$ for the next generation CMOS application. The sheet resistance of Ni Germanosilicide utilizing pure-Ni increased dramatically after the post-silicidation annealing at $600^{\circ}C$ for 30 min. Moreover, more degradation was found as the Ge fraction increases. However, using the proposed NiPt/Co/TiN tri-layer, low temperature silicidation and wide range of RTP process window were achieved as well as the improvement of the thermal stability according to different Ge fractions by the subsequent Co and TiN capping layer above NiPt on the $Si_{l-x}Ge_x$. Therefore, highly thermal immune Ni Germanosilicide up to $600^{\circ}C$ for 30 min is utilized using the NiPt/Co/TiN tri-layer promising for future SiGe based ULSI technology.

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Formation of a MnSixOy barrier with Cu-Mn alloy film deposited using PEALD

  • Moon, Dae-Yong;Hwang, Chang-Mook;Park, Jong-Wan
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.229-229
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    • 2010
  • With the scaling down of ultra large integrated circuits (ULSI) to the sub-50 nm technology node, the need for an ultra-thin, continuous and conformal diffusion barrier and Cu seed layer is increasing. However, diffusion barrier and Cu seed layer formation with a physical vapor deposition (PVD) method has become difficult as the technology node is reduced to 30 nm and beyond. Recent work on self-forming barrier processes using PVD Cu alloys have attracted great attention due to the capability of conformal ultra-thin barrier formation using a simple technique. However, as in the case of the conventional barrier and Cu seed layer, PVD of the Cu alloy seed layer will eventually encounter the difficulty in conformal deposition in narrow line trenches and via holes. Atomic layer deposition (ALD) has been known for its good step coverage and precise thickness control, and is a candidate technique for the formation of a thin conformal barrier layer and Cu seed layer. Conformal Cu-Mn seed layers were deposited by plasma enhanced atomic layer deposition (PEALD) at low temperature ($120^{\circ}C$), and the Mn content in the Cu-Mn alloys were controlled form 0 to approximately 10 atomic percent with various Mn precursor feeding times. Resistivity of the Cu-Mn alloy films decreased by annealing due to out-diffusion of Mn atoms. Out-diffused Mn atoms were segregated to the surface of the film and interface between a Cu-Mn alloy and $SiO_2$, resulting in self-formed $MnO_x$ and $MnSi_xO_y$, respectively. No inter-diffusion was observed between Cu and $SiO_2$ after annealing at $500^{\circ}C$ for 12 h, indicating an excellent diffusion barrier property of the $MnSi_xO_y$. The adhesion between Cu and $SiO_2$ was enhanced by the formation of $MnSi_xO_y$. Continuous and conductive Cu-Mn seed layers were deposited with PEALD into 32 nm $SiO_2$ trench, enabling a low temperature process, and the trench was perfectly filled using electrochemical plating (ECD) under conventional conditions. Thus, it is the resultant self-forming barrier process with PEALD Cu-Mn alloy film as a seed layer for plating Cu that has further potential to meet the requirement of the smaller than 30 nm node.

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Electrochemically Fabricated Alloys and Semiconductors Containing Indium

  • Chung, Yonghwa;Lee, Chi-Woo
    • Journal of Electrochemical Science and Technology
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    • 제3권3호
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    • pp.95-115
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    • 2012
  • Although indium (In) is not an abundant element, the use of indium is expected to grow, especially as applied to copper-indium-(gallium)-selenide (CI(G)S) solar cells. In future when CIGS solar cells will be used extensively, the available amount of indium could be a limiting factor, unless a synthetic technique of efficiently utilizing the element is developed. Current vacuum techniques inherently produce a significant loss of In during the synthetic process, while electrodeposition exploits nearly 100% of the In, with little loss of the material. Thus, an electrochemical process will be the method of choice to produce alloys of In once the proper conditions are designed. In this review, we examine the electrochemical processes of electrodeposition in the synthesis of indium alloys. We focus on the conditions under which alloys are electrodeposited and on the factors that can affect the composition or properties of alloys. The knowledge is to facilitate the development of electrochemical means of efficiently using this relatively rare element to synthesize valuable materials, for applications such as solar cells and light-emitting devices.

반도첼 레이저의 AuSn 합금 솔더를 사용한 p-side-down방식의 마운팅 (P-side-down mounting by using AuSn alloy solder of semiconductor laser)

  • 최상현;허두창;배형철;한일기;이천
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2003년도 추계학술대회 논문집 전기물성,응용부문
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    • pp.273-275
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    • 2003
  • 본 실험은 고출력 반도체 레이저의 p-side-down 마운팅용 솔더로서 AuSn 합금 솔더(80wt%:20wt%)의 적합성에 대해 연구하였다. $1{\mu}m$이하의 균일도로 폴리싱 된 Cu heat sink의 표면에 두께 $1{\mu}m$의 Ni로 코팅을 한다음, AuSn 다층박막은 e-beam 증착기로 AuSn 합금 솔더는 열증착기로 각각 증착하였다. 열처리는 산화 방지를 위해 $N_2$ 분위기에서 행하였으며, 동일한 압력으로 마운팅을 하였다. 표면의 거칠기와 형상은 AFM(Atomic Force Microscope)과 SEM(Scanning Electron Microscopy)으로 그리고 Au와 Sn의 성분비는 AES(Auger Electron Spectroscopy) 로 비교하였다. 또한 CW(연속발진)을 통한 L-I(Light-Current)측정을 통해 본딩상태를 비교하였다.

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