• Korean Journal of Fisheries and Aquatic Sciences
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• v.34 no.4
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• pp.348-354
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• 2001

This study was conducted to estimation of change characteristics for water quality by the dyke gate operation in the Keum River estuary. The estimation data made use of surveyed data in Keum River estuary by NERDI (National Fisheries Research and Development Institute) during $1990\~1999$. Shown to compare water quality changes at st. A and st. D in Figure 1, the concentrations of TSS, COD and nutrients at st. A were as high as about $2\~4$ times than those at st. D due to affection of fresh water discharge in the Keum River. The percentages of water quality change at surface water by dyke gate operation in the Keum River estuary were shown that TSS (Total Suspended Solid) was decrease to $56\%,\;47\%$ at st. A and D, and COD (Chemical Oxygen Demand) was increase to $68\%,\;71\%$ at st. A and D, respectively. The changes percentage of DIN (Dissolved Inorganic Nitrogen) by dyke gate operation in the Keum River estuary were increase high to $95\%$ at surface water and $7\sim30\%$ at bottom water, but those of DIP (Dissolved Inorganic Phosphorus) were increase to $2.8\sim8.6\%$ at surface water and $28\%$ at bottom water. The range of fluctuation for water quality at each station by dyke gate operation has shown that salinity and TSS are little better than before dyke gate operation, but COD show highly fluctuation. Also we studied estimation of characteristics of water quality change by the season, COD was increased except the summer, TSS was decreased to all season. DIN was increased to about $61\sim172.1\%$ for all season, but DIP was increased to the spring and decreased to the autumn, DIN enrichment in the estuary by dyke gate operation are interpreted to improvement of organic matter decomposition and nitrification by increasing the residence time and to increase nutrient flux in sediments due to decreasing dissolved oxygen and increasing a deposit matter.

• Journal of IKEEE
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• v.15 no.2
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• pp.143-148
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• 2011

MOS (Metal-Oxide Semconductor) devices among the most sensistive of all semiconductors to radiation, in particular ionizing radiation, showing much change even after a relatively low dose. The necessity of a radiation dosimeter robust enough for the working environment has increased in the fields of aerospace, radio-therapy, atomic power plant facilities, and other places where radiation exists. The power MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor) has been tested for use as a gamma radiation dosimeter by measuring the variation of threshold voltage based on the quantity of dose, and a maximum total dose of 30 krad exposed to a $^{60}Co$ ${\gamma}$-radiation source, which is sensitive to environment parameters such as temperature. The gate oxide structures give the main influence on the changes in the electrical characteristics affected by irradiation. The variation of threshold voltage on the operating temperature has caused errors, and needs calibration. These effects can be overcome by adjusting gate oxide thickness and implanting impurity at the surface of well region in MOSFET.

• Journal of Power Electronics
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• v.16 no.2
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• pp.769-777
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• 2016

This work focuses on current sharing between punch-through insulated gate bipolar transistors (IGBTs) connected in parallel and evaluates the mechanisms that allow overall current balancing. Two different control strategies are presented. These strategies are based on the modification of transistor gate-emitter control voltage V_GE by using an active gate driver circuit. The first strategy relies on the calculation of the average value of the current flowing through all parallel-connected IGBTs. The second strategy is proposed by the authors on the basis of a current cross reference control scheme. Finally, the simulation and experimental results of the application of the two current sharing control algorithms are presented.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.578-578
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• 2012

Graphene, a flat one-atom-thick two-dimensional layer of carbon atoms, is considered to be a promising candidate for nanoelectronics due to its exceptional electronic properties. Most of all, future nanoelectronics such as flexible displays and artificial electronic skins require low cost manufacturing process on flexible substrate to be integrated with high resolutions on large area. The solution based printing process can be applicable on plastic substrate at low temperature and also adequate for fabrication of electronics on large-area. The combination of printed electronics and graphene has allowed for the development of a variety of flexible electronic devices. As the first step of the study, we prepared the gate electrodes by printing onto the gate dielectric layer on PET substrate. We showed the performance of graphene field-effect transistor with electrohydrodynamic (EHD) inkjet-printed Ag gate electrodes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.1
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• pp.11-18
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• 2019

In this paper, we consider interferences from other automobile pulse radars using same frequency spectrum. In order to eliminate the interference, we propose the PN code modulation method. This method uses the cross-correlation between PN codes with different seed. The ROC performance is used for comparing the proposed detector to conventional method. And the proposed detector can decide the present or absent of targets and measure the range of the targets by using memory buffer of range gate. Especially, we use false alarm probability for all range gates. That is the false alarm if in any one range gate the false alarm occurs. From the simulation result, we can see that the proposed detector with using PN code is not influenced by interferences.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.56-62
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• 1999

All the cells on the whole memory array or a block of the memory array in the Flash EEPROM's are erased at the same time using Fowler-Nordheim (FN) tunneling. some of the cels are often overerased since the tunneling is not a self-limited process. In this paper, the optimum doping concentration of the floating gate solve the overerase problem has been studied. For these studies, N-type MOSFETs and MOS capacitors with various doping concentrations of the gate polysilicon have been fabricated and their electrical characteristics have been measured and analyzed. As the results of the experiment, it has been found that the overerase problem can be prevented if the doping concentration of the floating gate is low enough (i.e. below $1.3{\times}10^{18}/cm^3$). It is because the potential difference between the floating gate and the source is lowered due to the formation of the depletion layer in the floating gate and thus the erasing operation stops by itself after most of the electrons stored in the floating gate are extracted. On the other hand, the uniformity of the Vt and the gm has been significantly poor if the coping concentration of the floating, gate is too much lowered (i.e. below $1.3{\times}10^{17}/cm^3$), which is believed to be due to nonuniform loss of the dopants from the nonuniform segregation in the floating gate. Consequently, the optimum doping concentration of the floating gate to suppress the overerase problem and get the uniform Vt and has been found to range from $1.3{\times}10^{17}/cm^3$ to $1.3{\times}10^{18}/cm^3$ in the Flash EEPROM.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.3
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• pp.83-94
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• 2017

There is a two lane ECTS(Electronic Toll Collection System) that users can pass with 80kph high speed in SeoBusan Tall Gate. This system to be combined two hi-pass lanes for removing meddle-island have been operated successfully. But, the appearance of two Lane ETCS makes toll gate more complicated, so it is very important how to arrange effectively various tolling lanes. This study was trying to evaluate lane configuration for minimizing speed and speed deviation among all kinds of lanes including two Lane ETCS in seoul toll gate. That is, we selected all scenarios to be happened actually, and evaluated them using micro traffic simulation model (VISSIM). The results of this study showed that each alternative had a very different speed and speed deviation by lane each other, so we will be able to achieve effective operation and configuration of lanes in toll gate using scenario methodology.

• Journal of Korean Institute of Industrial Engineers
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• v.29 no.2
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• Korean Institute of Interior Design Journal
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• v.20 no.4
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• pp.74-82
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• 2011

All the phenomena and subjects of nature and society are within correlation interconnection, and they are inseparably connected one another. The elements of this interaction can be found out through the concept of transparency in the space composition of Korean traditional architecture. This study is focusing on the access space, in other words, a gate-house that is a buffer zone playing a process role up to the main space among successive spaces. It was chosen to be the subject of the study since it strengthens convergence into the main building and with the effect connecting spaces, it could show well the spatial possibility of transparency. Besides, the subject of the study is limited to the Moonru Multi roofs that improves the functionality of spaces between gate-houses, and it is intended to progress contents by comparative analysis of two kinds such as Seo Won gate-house and temple gate-house. Korean traditional architecture places emphasis on harmony within the whole spaces. There are intimate relations between surrounding environment, external spaces and internal spaces, and it is important understand the spatial relations according to the shape appearing through interactions of parts in the whole spaces. In conclusion, the Moonru Multi roofs is analyzed with the method of extracting the concept that is contained in the frame of analysis and through ecological views through a visible and structural method. It can be understood what kinds of method for communication were used for ancestors to recognize and use spaces with the deduced concept through the analysis of the Moonru Multi roofs with different character.