• 전자공학회논문지B
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• 제31B권9호
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• 공학논문집
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• 제2권1호
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• pp.31-37
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• 1997

본 논문에서의 ALU는 덧셈, 뺄셈, 1증가, 1 감소, 2의 보수 등의 산술 연산을 수행하는 산술 연산 회로, 논리합, 논리곱, 배타논리합, 부정과 같은 논리 연산을 수행하는 논리 연산 회로, 쉬프트 연산 및 산술 혹은 논리 연산 회로의 연산 결과를 데이터 버스로 전송하는 기능을 담당하는 쉬프터로 구성되며, 이러한 기본적인 ALU 기능과 관련된 명령어는 Z80 명령어에서 추출하여 ALU의 내부 회로를 설계하였고, 이 설계된 회로를 그래픽 화면으로 구성하여 데이터의 연산이 ALU 내부에서 어떤 과정과 경로를 거쳐 수행되는 가를 비트 및 논리 게이트 단위까지 처리하여 ALU 구조와 단계별 연산 과정을 그래픽 형태로 학습하는 교육 시스템이다.

• Nuclear Engineering and Technology
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• 제48권2호
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• pp.470-481
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• 2016

Field-programmable gate arrays (FPGAs) have received much attention from the nuclear industry as an alternative platform to programmable logic controllers for digital instrumentation and control. The software aspect of FPGA development consists of several steps of synthesis and refinement, and also requires verification activities, such as simulations that are performed individually at each step. This study proposed an integrated software-testing framework for simulating all artifacts of the FPGA software development simultaneously and evaluating whether all artifacts work correctly using common oracle programs. This method also generates a massive number of meaningful simulation scenarios that reflect reactor shutdown logics. The experiment, which was performed on two FPGA software implementations, showed that it can dramatically save both time and costs.

• 한국통신학회논문지
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• 제25권6A호
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• pp.862-869
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• 2000

스위칭 시스템에서 버퍼는 라우팅시 신호간의 충돌을 방지하기 위해 반드시 필요하다. 광 스위칭 시스템에서도 단순한 광 교차 접속(OXC) 이상의 교환 및 라우팅을 수행하기 위해서는 광 버퍼를 필요로 한다. 오늘날 광전송 시스템 및 광 네트워크는 WDM을 기반으로 형성되어 가고 있으며 따라서 광 스위칭 역시 WDM 기술에 기반을 둘 것이고 이에 필요한 광 버퍼도 WDM 신호를 처리할 수 있어야 한다. WDM 스위칭 시스템에서 동시에 동일 가입자로 라우팅된 WDM 신호들을 순차적으로 출력시키기 위해 WDM 광 출력 버퍼를 필요로 한다. 본 논문에서는 기존의 발표된 WDM 광 출력 버퍼에 비해 구조, 하드웨어, SNR 및 BER 특성이 개선된 새로운 구조의 WDM 광 출력 버퍼를 제안한다. 제안한 버퍼에 대한 특성 분석결과, 새로운 구조의 버퍼는 버퍼를 구성하는 광 게이트(반도체 광 증폭기)의 이득 ON-OFF 비율(Contrast ratio)이 30dB인 경우, BER 10-9을 만족하면서 255개의 WDM셀을 저장할 수 있음을 알 수 있다.

• 대한전자공학회논문지
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• 제17권6호
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• pp.51-57
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• 1980

스위칭함수는 만능게이트인 NAND gate를 이용하여 3단논리회로로 구성될 수 있으며, 3단논리회로이면서 책의 입력값 만을 허용하는 회로를 TANT(three-level AND-NOT network with true Inputs) 회로망으로 정의하여 사용하고 있다. 본 연구는 TANT회로망의 설계에 있어 최적화과정의 새 방법을 제안한 것으로 CPPI 혹은 EPPㅑ를 만들면서 C-C 표를 쓰지 않고 직접 최적의 TANT 회로망을 구하는 방법이다. 본 알고리즘은 스위칭함수의 입력변수가 4개 혹은 5개까지 수작업(수작업)으로 가능하지만 그 이상의 것은 컴퓨터에 의해 처리될 수 있으며 이를 위해 CAD(computer aided design) 소프트웨어 패키지를 FORTRAN IV로 작성하였다.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.331-331
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• 2009

Hafnium oxide ($HfO_2$) attracted by one of the potential candidates for the replacement of si-based oxides. For applications of the high-k gate dielectric material, high thermodynamic stability and low interface-trap density are required. Furthermore, the amorphous film structure would be more effective to reduce the leakage current. To search the gate oxide materials, metal-insulator-metal (MIM) capacitors was fabricated by pulsed laser deposition (PLD) on indium tin oxide (ITO) coated glass with different oxygen pressures (30 and 50 mTorr) at room temperature, and they were deposited by Au/Ti metal as the top electrode patterned by conventional photolithography with an area of $3.14\times10^{-4}\;cm^2$. The results of XRD patterns indicate that all films have amorphous phase. Field emission scanning electron microscopy (FE-SEM) images show that the thickness of the $HfO_2$ films is typical 50 nm, and the grain size of the $HfO_2$ films increases as the oxygen pressure increases. The capacitance and leakage current of films were measured by a Agilent 4284A LCR meter and Keithley 4200 semiconductor parameter analyzer, respectively. Capacitance-voltage characteristics show that the capacitance at 1 MHz are 150 and 58 nF, and leakage current density of films indicate $7.8\times10^{-4}$ and $1.6\times10^{-3}\;A/cm^2$ grown at 30 and 50 mTorr, respectively. The optical properties of the $HfO_2$ films were demonstrated by UV-VIS spectrophotometer (Scinco, S-3100) having the wavelength from 190 to 900 nm. Because films show high transmittance (around 85 %), they are suitable as transparent devices.

• 마이크로전자및패키징학회지
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• 제14권3호
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• pp.15-20
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• 2007

플라스틱 기판에 적용이 가능한 최대 공정온도 $270^{\circ}C$ 이하에서 ZnO-TFT 소자를 제작하였다. ZnO-TFT 소자는 bottom gate 구조로 제작되었으며, ICP-CVD로 형성된 $SiO_2$ 산화물 게이트 공정을 제외하고는 모든 박막증착 공정은 RF-magnetron sputtering process를 이용하였다. ZnO 박막은 Ar과 $O_2$ gas 유량의 비율에 따라 여러 가지 조건에서 RF-magnetron sputtering 시스템을 이용하여 상온에서 증착하였다. Ar과 $O_2$ gas의 비율에 따라 제작된 TFT 소자는 모두 enhancement 모드의 소자특성을 나타내었고, 또한 가시광선영역에 있어 80% 이상의 높은 투과율을 보였다. ZnO 증착시 순수 Ar을 사용하여 제작된 ZnO-TFT의 경우에, $1.2\;cm^2/Vs$의 field effect mobility, 8.5 V의 threshold voltage, 그리고 $5{\times}10^5$의 높은 on/off ratio, 1.86 V/decade의 swing voltage로 가장 우수한 전기적 특성을 보였다.

• Journal of Biosystems Engineering
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• 제34권2호
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• pp.95-105
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• 2009

A method was proposed which employed control of the drop location of fertilizer particles on a spinner disc to optimize the spread pattern uniformity. The system contained an optical sensor as a feedback mechanism, which measured discharge velocity and location, as well as particle diameters to predict a spread pattern of a single disc. Simulations showed that the feed gate adaptation algorithm produced high quality patterns for any given application rate in the dual disc spreader. The performance of the feed gate control method was assessed using data collected from a Sulky spinner disc spreader. The results showed that it was always possible to find a spread pattern with an acceptable CV lower than 15%, even though the spread pattern was obtained from a rudimentary flat disc with straight radial vanes. A mathematical optimization method was used to find the initial parameter settings for a specially designed experimental spreading arrangement, which included the feed gate control system, for a given flow rate and swath width. Several experiments were carried out to investigate the relationship between the gate opening and flow rate, disc speed and particle velocity, as well as disc speed and predicted landing location of fertilizer particles. All relationships found were highly linear ($r^2$ > 0.96), which showed that the time-of-flight sensor was well suited as a feedback sensor in the rate and uniformity controlled spreading system.

• 한국광학회:학술대회논문집
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• 한국광학회 1998년도 제15회 광학 및 양자전자 학술발표회 논문집
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• pp.192-193
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• 1998

At Rutherford Appleton Laboratory(RAL), a high-repetition rate ps exicmer laser-plasma x-ray source has been developed for x-ray lithography with a calibrated output of up to 1 watt X-ray average power at 1nm wavelength. In a previous reports this compact x-ray source was used to print 0.18$\mu$m lines for a gate on Si-FET devices and deep three-dimensional structure with 100$\mu$m length, 25$\mu$m width, and 48 $\mu$m depth for a nanotechnology. The deep X-ray lithography is called as LIGA thchnology and getting a wide interest as a new technology for a nano-device. In this report all this works are summarized.