• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.937-940
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• 2000

This paper describes expandable 4 bit ALU IC using adiabatic and dynamic CMOS circuit technique. It was designed so that the integrated circuit may have the function which is equivalent to HC181 which is CMOS standard logic IC for the comparison, and it was fabricated using a standard 1.2${\mu}$ CMOS process. As the result, the IC has shown that it operates perfectly on all function modes. The power dissipation is 2 order lower than that of HC 181.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.285-291
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• 2001

An 8-b$\times$8-b adiabatic pipelined multiplier is designed. Simplified four phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and are integrated using 0.6${\mu}{\textrm}{m}$ CMOS technology. The efficiency of proposed supply clock generator is better than the previous one by 4~11%. Simulation results show that the power consumption of adiabatic pipelined multiplier is reduced by a factor of 2.6~3.5 compared to a conventional pipelined CMOS multiplier.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.349-352
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• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.341-352
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• 2012

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven and low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce operating power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18 2m CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1 pJ/cycle when working at the frequency of 403 MHz, which is only 36% of PE with the conventional static CMOS gates. The measurement results show that the test chip can work as high as 609 MHz with the energy dissipation of 2.1 pJ/cycle.

• 한국신재생에너지학회:학술대회논문집
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• 2007.11a
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• pp.424-428
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• 2007

In the current most tool using heat and mass balance in a coal gasifier is dependent on commercial code such as STANJAN, CHEMKIN. However, in order to keep the self-reliance technology, it is necessary to develop the original design tool available for comprehension and analysis on the spot. So in this study, its own heat and mass balance program is developed on the assumption that the process in a coal gasifier is adiabatic and quasi-equilibrium. The mass balance is calculated by using the chemical equilibrium principle. Also the heat and mass balance according to main operating factors such as temperature, pressure and O2/Coal ratio, was carried in this tool. This heat and mass balance was verified on the basis of the results simulated in STANJAN, commercial codes using similar logic.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.556-558
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• 2004

최근 VLSI 설계 분야에서, 단열 논리는 에너지 효율성이 뛰어난 저전력 설계 기술 중 하나로 각광 받고 있다. 이러한 단열 논리는 기존의 저전력 회로 설계를 위해 사용되었던 CMOS 논리들을 서서히 대체해 나갈 컷으로 기대되고 있다. 하지만 않은 단열 논리들의 제시에도 불구하고, 기존의 CMOS논리들을 단열 논리로 대체하는 기법에 관한 연구는 거의 없는 실정이다. 이 논문에서는 래치형 패스 트랜지스터 단열 논리(LPAL)와 이를 이용한 저전력 설계 기법을 소개하였다. 래치형 패스 트랜지스터 단열 논리는 기존의 단열 논리들이 가지고 있는 단정을 해결하고, 보다 저전력 지향적으로 CMOS논리를 대체 할 수 있다는 장점을 가진다.