• Title/Summary/Keyword: Addressable

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Built-in self test for testing neighborhood pattern sensitive faults in content addressable memories (Content addressable memory의 이웃패턴감응고장 테스트를 위한 내장된 자체 테스트 기법)

  • 강용석;이종철;강성호
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.8
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    • pp.1-9
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    • 1998
  • A new parallel test algorithm and a built-in self test (BIST) architecture are developed to test various types of functional faults efficiently in content addressable memories (CAMs). In test mode, the read oepratin is replaced by one parallel content addressable search operation and the writing operating is performed parallely with small peripheral circuit modificatins. The results whow that an efficient and practical testing with very low complexity and area overhead can be achieved.

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An Addressable Type Smoke Detect System Implementation to detect the Fire on a Ship (선박화재감지를 위한 Addressable Type Smoke Detect System 구현)

  • Kim, Tai-Suk;Kim, Jong-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.12
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    • pp.2543-2548
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    • 2011
  • The Smoke Detect System is setup to extinguish early a fire on the large ship like as the cargo ship and Bulk Carrier at sea. The Addressable Type Smoke Detect System that keeps the advantages and dispenses with the disadvantages of the existing conventional type system is composed of only one electrical cords. In this paper, we make the Smoke Detect System of an addressable type and implement to control it using ATmega Micro-controller and evaluate it.

A Study on the Necessity of an Addressable Emergency Broadcasting System to Improve Evacuation Performance (피난성능향상을 위한 주소형 비상방송시스템의 필요성에 관한 연구)

  • Kim, Si-Kuk;Lee, Min-Yong;Lee, Chun-Ha
    • Fire Science and Engineering
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    • v.29 no.5
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    • pp.14-22
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    • 2015
  • This thesis is based on the study of necessity of an addressable emergency broadcasting system to improve evacuation performance in order to minimize human casualty by avoiding the initial evacuation after fires such as the multi-unit dwelling fire in Euijeongbu in 2015. To minimize the damage from fire generated in a complex internal structure such as modern buildings, introduction of adaptable emergency broadcasting system, could increase the efficiency of evacuation by preventing of initial mistaken evacuation directions by alerting the accurate location of fire to the occupants, is needed. As such, this study designed and fabricated the addressable emergency broadcasting system using the existing addressable system. Its performance was compared with a conventional emergency broadcasting system to confirm the necessity of the addressable emergency broadcasting system to improve evacuation performance. The test result showed that the addressable emergency broadcasting system decreased the evacuation time by up to 30.3% in a small-scale model evacuation performance experiment, up to 54.6% in a hallway evacuation performance experiment compared to the conventional emergency broadcasting system.

Variation-tolerant Non-volatile Ternary Content Addressable Memory with Magnetic Tunnel Junction

  • Cho, Dooho;Kim, Kyungmin;Yoo, Changsik
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.3
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    • pp.458-464
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    • 2017
  • A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

Design of an Analog Content Addressable Memory Implemented with Floating Gate Treansistors (부유게이트 트랜지스터를 이용한 아날로그 연상메모리 설계)

  • Chai, Yong-Yoong
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.50 no.2
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    • pp.87-92
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    • 2001
  • This paper proposes a new content-addressable memory implemented with an analog array which has linear writing and erasing characteristics. The size of the array in this memory is $2{\times}2$, which is a reasonable structure for checking the disturbance of the unselected cells during programming. An intermediate voltage, Vmid, is used for preventing the interference during programming. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We simulate the function of the mechanism by means of Hspice with 1.2${\mu}m$ double poly CMOS parameters of MOSIS fabrication process.

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Design and Verification of Addressable Automatic Fire Detection System for Existing Apartments (기존아파트의 적용성을 고려한 주소형 자동화재탐지설비의 설계 및 검증)

  • An, Hyunsung
    • Land and Housing Review
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    • v.13 no.4
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    • pp.105-114
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    • 2022
  • Non-fire activated fire alarms caused by such actions as cigarette smoke, cooking, and high humidity are fire safety risk factors. In such instances, it is important to quickly locate and replace the actuated detector. However, it is difficult to locate those detectors because most do not have an address function. While new apartments can incorporate addressable fire alarm detectors, in existing apartments there are limitations in converting over to addressable detectors due to cost and power line issues. This study developed an efficient address function for fire alarms in existing apartments. The newly developed system consists of the existing receiver, and a proposed addressable repeater and detector. Utilizing an experimental setup, the performance of the proposed address monitoring system was confirmed to be stable and compatible with the receiver and existing detectors.

A Memory-Efficient Two-Stage String Matching Engine Using both Content-Addressable Memory and Bit-split String Matchers for Deep Packet Inspection (CAM과 비트 분리 문자열 매처를 이용한 DPI를 위한 2단의 문자열 매칭 엔진의 개발)

  • Kim, HyunJin;Choi, Kang-Il
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39B no.7
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    • pp.433-439
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    • 2014
  • This paper proposes an architecture of two-stage string matching engine with content-addressable memory(CAM) and parallel bit-split string matchers for deep packet inspection(DPI). Each long signature is divided into subpatterns with the same length, where subpatterns are mapped onto the CAM in the first stage. The long pattern is matched in the second stage using the sequence of the matching indexes from the CAM. By adopting CAM and bit-split string matchers, the memory requirements can be greatly reduced in the heterogeneous string matching environments.

Design of a scalable general-purpose parallel associative processor using content-addressable memory (Content-Addressable Memory를 이용한 확장 가능한 범용 병렬 Associative Processor 설계)

  • Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.2 s.344
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    • pp.51-59
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    • 2006
  • Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

A Study on the Design and Fabrication of Content Addressable Memory (연상메모리 설계 및 제작에 관한 연구)

  • 박상봉;박노경;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.2
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    • pp.145-154
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    • 1991
  • In this dissertation, the same reading and writing operation of general SRAM, the algonthm and hardware of 8 bit $\times$16 word CAM(Content Addressable Memory) which carry out the parallel that search is presented. The designed CAM chip consists of five functional blocks (CAM cell array, Address Deceden, Address Encoden. Data Selector, Sense Amplifier). The smulation is performed using logic smmulator on Apollo workstation and PSPICE eitcut simulation on PC/AT. The designed CAM was fabricated by 3um CMOS N Well process (ETRI) design nitles and testing was performed.

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Actively Addressable Carbon NanoTube Emitters for Field Emission Display

  • Song, Yoon-Ho;Hwang, Chi-Sun;Kim, Kwang-Bok
    • 한국정보디스플레이학회:학술대회논문집
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    • 2003.07a
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    • pp.194-197
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    • 2003
  • The actively addressable carbon nanotube (CNT) emitters have been studied for stable and low-voltage driving field emission display (FED). The a-Si TFT and screen-printed CNT emitters were successfully integrated to fabricate the diode type active-matrix cathode and FED panel. Also, we propose a new FED architecture based on the actively controlled triode CNT emitters showing the properties of ideal triode type cathode with electron beam focusing effect.

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