• The KIPS Transactions:PartC
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• v.10C no.5
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• pp.549-556
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• 2003

In this paper, we describe security policy protocol to provide end-to-end IPSec security service that considers characteristics of NAT-PT. NAT-PT is describing IP address translation and protocol translation for communication on heterogeneous IP network by one of the technology that is proposed by IETF to provide communication between IPv4 and IPv6 network in transitional step to evolve by IPv6 network to IPv4 network. But NAT-PT has the limitation on security one of the essential requirement of Internet. Therefore, we propose the extended security protocol that offers a security policy negotiation that should be achieved for the first time to provide end-to-end IPSec security service that considers NAT-PT in this paper.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.21-30
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• 2009

Fusion flash memory such as OneNAND$^{TM}$ is popular as a ubiquitous storage device for embedded systems because it has advantages of NAND and NOR flash memory that it can support large capacity, fast read/write performance and XIP(eXecute-In-Place). Besides, OneNAND$^{TM}$ provides not only advantages of hybrid structure but also multi-block erase function that improves slow erase performance by erasing the multiple blocks simultaneously. But traditional NAND Flash Translation Layer may not fully support it because the garbage collection of traditional FTL only considers a few block as victim block and erases them. In this paper, we propose an Erase Group Flash Translation Layer for improving multi-block erase function. EGFTL uses a superblock scheme for enhancing garbage collection performance and invalid block management to erase multiple blocks simultaneously. Also, it uses clustered hash table to improve the address translation performance of the superblock scheme. The experimental results show that the garbage collection performance of EGFTL is 30% higher than those of traditional FTLs, and the address translation performance of EGFTL is 5% higher than that of Superblock scheme.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.168-174
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• 2006

In this paper, we propose an architecture for communication between the IPv4-based UA and the IPv6-based UA in IMS based Mobile Networks, and design and implement the IMS protocol Translator for verification of the architecture. For the design of the internetworking between the IPv4 and the IPv6, we analyze the transition mechanisms and investigate the protocol translator. The IMS protocol translator is composed of the IMS-ALG(IP Multimedia Subsystem - Application Level Gateway) and TrGW(Translation Gateway), and the conformance of these components are verified by experiments.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.117-124
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• 2010

Appling centralized network management architecture SNMP(Simple Network Management Protocol) to wireless networks causes the network overhead, NAT(Network Address Translation) problem on AP, and performance degradation of mobile nodes. In this paper, we propose an integrated management scheme for wired and wireless networks using mobile agents in order to solve above problems. In our proposed scheme, SNMP is applied to manage wired networks and MAs of SNMP are implemented in APs or wireless nodes to manage wireless networks. In addition, we propose a method to reduce the redundant OID information within SNMP response messages. Through the analysis, we show that our proposal resolves the given problems and reduces the processing delay of the wireless nodes.

• Journal of Korea Spatial Information System Society
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• v.5 no.1 s.9
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• pp.75-81
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• 2003

In spite of widely deploying information broadcasting services based on Internet, there are some limitations to use them due to the bound of Internet protocol. In this paper, a new Internet broadcasting technology for access network and Location Based Services are proposed by employing IP address translation function in base station. There are some advantages such as, no need to allocate IP address to receiver no need to know web site address, and reduction of traffic for server and network.

• The Transactions of the Korea Information Processing Society
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• v.3 no.1
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• pp.118-126
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• 1996

Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.1 no.1
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• pp.23-35
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• 1983

In its global meaning language translation refers to the process whereby a program which is executable in one computer can be executed in another computer directly to obtain the same result. There are four different ways of approaching translation. The first way is translation by a Translator or a Compier, the second way is Interpretation, the third way is Simulation, the last way is Emulation. This paper introduces the M-C Translator which was designed as the first way of translation. The MUSS 80 language (the subsystem of the UNIVAC Solid State 80 S-4 assembly language system) was chosen as the source language which includes forty-three instructions, using the CYBER COMPASS as the object language. The M-C translator is a two pass translator and is a two pas translator and es written in Fortran Extended language. For this M-C Translation, seven COMPASS subroutines and a set of thirty-five macros were prepared. Each executable source instruction corresponds to a macro, so it will be a macro instruction within the object profram. Subroutines are used to retain and handle the source data representation the same way in the object program as in the source system, and are used to convert the decimal source data into the equivalent binary result into the equivalent USS-80digits before and after arithmetic operations. The source instructions can be classified into three categories. First, therd are some instructions which are meaningless in the object system and are therefore unnecessary to translate, and the remaining instructions should be translated. Second, There are some instructions are required to indicate dual address portions. Third, there are Three instructions which have overflow conditions, which are lacking in the remaining instructions. The construction and functions of the M-C Translator, are explained including some of the subroutines, and macros. The problems, difficulties and the method of solving them, and easier features on this translation are analysed. The study of how to save memory and time will be continued.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.3
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• pp.371-375
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• 2010

SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.21-31
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• 2010

Recently e-business such as online financial trade and online shopping using mobile computes are widely spread. Most of mobile computers use NAND flash memory-based storage devices for storing data. Flash memory storage devices use a software called flash translation layer to translate logical address from a file system to physical address of flash memory by using mapping tables. The legacy FTLs have a problem that they must maintain very large mapping tables in the RAM. In order to address this issues, in this paper, we proposed a new caching scheme of mapping tables. We showed through the trace-driven simulations that the proposed caching scheme reduces the space overhead dramatically but does not increase the time overhead. In the case of online transaction workload in e-business environment, in particular, the proposed scheme manifests better performance in reducing the space overhead.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.5
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• pp.1151-1160
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• 2016

A TrustZone-based rootkit detecting solution using a secure timer ensures the integrity of monitoring system, because ARM TrustZone technology provides isolated environments from a monitored OS against intercepting and modifying invoke commands. However, it is vulnerable to transient attack due to periodic monitoring. Also, Address Translation Redirection Attack (ATRA) cannot be detected, because the monitoring is operated by using the physical address of memory. To ameliorate this problem, we propose a snoop-based kernel introspection system. The proposed system can monitor a kernel memory in real-time by using a snooper, and detect memory-bound ATRA by introspecting kernel pages every context switch of processes. Experimental results show that the proposed system successfully protects the kernel memory without incurring any significant performance penalty in run-time.