• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.913-916
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• 2009

This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with $0.35-{\mu}m$ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.

• Journal of Semiconductor Engineering
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• v.2 no.3
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• pp.136-141
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• 2021

This paper analyzes the tree expansion for multiple-input multiple-output (MIMO) detection in the viewpoint of hardware implementation. The tree expansion is to calculate path metrics of child nodes performed in every visit to a node while traversing the detection tree. Accordingly, the tree-expansion unit (TEU), which is responsible for such a task, has been an essential component in a MIMO detector. Despite the paramount importance, the analyses on the TEUs in the literature are not thorough enough. Accordingly, we further investigate the hardware complexity of the TEUs to suggest a guideline for selection. In this paper, we focus on a pair of major ways to implement the TEU: 1) a full parallel realization; 2) a transformation of the formulae followed by common subexpression elimination (CSE). For a logical comparison, the numbers of multipliers and adders are first enumerated. To evaluate them in a more practical manner, the TEUs are implemented in a 65-nm CMOS process, and their propagation delays, gate counts, and power consumptions were measured explicitly. Considering the target specification of a MIMO system and the implementation results comprehensively, one can choose which architecture to adopt in realizing a detector.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.223-225
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• 2021

Modular multiplication is a key operation for point scalar multiplication of ECC, and is the most important factor affecting the performance of ECC processor. This paper describes a design of a 256-bit modular multiplier that adopts 3-way Toom-Cook multiplication algorithm and modified fast reduction algorithm. One 90-bit multiplier and three 264-bit adders were used to optimize the hardware size and the number of clock cycles required. The modular multiplier was verified by implementing it using Zynq UltraScale+ MPSoC device and the modular multiplication operation takes 15 clock cycles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.715-722
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• 2010

This paper describes a hardware design of hash function processor which implements Korean Hash Algorithm Standard HAS-160. The HAS-160 processor compresses a message with arbitrary lengths into a hash code with a fixed length of 160-bit. To achieve high-speed operation with small-area, arithmetic operation for step-operation is implemented by using a hybrid structure of 5:3 and 3:2 carry-save adders and carry-select adder. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency. The designed HAS-160 processor is verified by FPGA implementation, and it has 17,600 gates on a layout area of about $1\;mm^2$ using a 0.35-${\mu}m$ CMOS cell library.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.1
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• pp.78-83
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• 2014

This paper suggest an effective idea to implement an low area multi-mode one dimension transform block of HEVC(High Efficiency Video Coding). The time consuming multiplier path is designed to operate on low frequency. Normal multipliers dealing with variable operands are replaced with smaller constant multipliers which do the product with constant coefficient and variable only using shifters and adders. This scheme increases total multiplier counts but entire areas are reduced owing to smaller area of constant multiplier. Idle cycles caused by doubled multipliers enable to use multi-cycle paths on the cycle eating multiplier data path. Operating frequency is lowered by multi-cycle path but total throughput is maintained. This structure is implemented with TSMC 0.18 CMOS process library, and operated on 186MHz frequency to process a 4k($3840{\times}2160$) image. Max operating frequency is 300MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.50-55
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• 2008

As more DSP functionalities are integrated into an embedded mobile device, power consumption and device reliability have emerged as crucial issues. As the complexity of mobile embedded designs increases very rapidly, verifying the functionality of the mobile devices has become extremely difficult. Therefore, designs with error (fault) tolerance are often required since these capabilities will enable the design to operate properly even with some existence of errors. However, designs with fault tolerance may suffer from significant power overhead since fault tolerance is often achieved by resource replication. In this paper, we propose a low power and fault tolerant MAC (multiply-and-accumulate) design. The proposed MAC design is based on multiple barrel shifters since MAC designs with barrel-shifters and adders are known to be excellent in terms of power consumption.

• Journal of IKEEE
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• v.13 no.4
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• pp.110-115
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• 2009

The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation. The quarter-pixel interpolation is achieved using 6-tap horizontal or vertical FIR filters for luminance data and bilinear FIR filters for chroma data. We propose the architecture for interpolation of luminance and chroma data in H.264 decoders. It is composed of dual-channel pipelined processing elements and can interpolate integer-, half- and quarter-pixel data. The number of the processing cycles is different depending on the position. The processing elements are composed of adders and shifters to reduce the complexity while the accuracy of the pixel data are maintained. We design interpolators for luminance and chroma data using Verilog-HDL and verify the function and performance by implementing using an FPGA.

• Journal of Broadcast Engineering
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• v.11 no.3 s.32
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• pp.320-325
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• 2006

An image is partitioned into non-overlapping $8{\times}8$ blocks fer JPEG compression. A scan order converter is placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. In general, its architecture requires two line memories for storing eight lines separately to allow the concurrent memory access by both the camera and JPEG processors. Although such architecture is simple to be implemented, it can be inefficient due to too excessive memory requirement as the image resolution increases. However, no deterministic addressing equation has been developed for scan conversion. In this paper, an effective memory addressing algorithm is proposed that can be devised only by adders and subtracters to implement a scan converter based on the single line memory.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.12
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• pp.1539-1547
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• 1999

캐리-세이브 가산기 (CSA)는 회로 설계 과정에서 빠른 연산 수행을 위해 가장 널리 이용되는 연산기 중의 하나이다. 그러나, 현재까지 산업체에서 CSA를 이용한 설계는 설계자의 경험에 따른 수작업에 의존하고 있고 그 결과 최적의 회로를 만들기 위해 매우 많은 시간과 노력이 소비되고 있다. 이에 따라 최근 CSA를 기초로 하는 회로 합성 자동화 기법에 대한 연구의 필요성이 대두되고 있는 상황에서, 본 논문은 연산 속도를 최적화하는 효율적인 CSA 할당 알고리즘을 제안한다. 우리는 CSA 할당 문제를 2단계로 접근한다: (1) 연산식의 멀티 비트 입력들만을 고려하여 최소 수행 속도 (optimal-delay)의 CSA 트리를 할당한다; (2) (1)에서 구한 CSA 트리의 수행 속도 증가가 최소화 (minimal increase of delay) 되는 방향으로 CSA들의 캐리 입력 포트들에 나머지 싱글 비트 입력들을 배정한다. 실제 실험에서 우리의 제안된 알고리즘을 적용하여 연산식들의 회로 속도를 회로 면적의 증가 없이 상당한 수준까지 줄일 수 있었다.Abstract Carry-save-adder (CSA) is one of the most widely used implementations for fast arithmetics in industry. However, optimizing arithmetic circuits using CSAs is mostly carried out by the designer manually based on his/her design experience, which is a very time-consuming and error-prone task. To overcome this limitation, in this paper we propose an effective synthesis algorithm for solving the problem of finding an allocation of CSAs with a minimal timing for an arithmetic expression. Specifically, we propose a two step approach: (1) allocating a delay-optimal CSA tree for the multi-bit inputs of the arithmetic expression and (2) determining the assignment of the single-bit inputs to carry inputs of the CSAs which leads to a minimal increase of delay of the CSA tree obtained in step (1). For a number of arithmetic expressions, we found that our approach is very effective, reducing the timing of the circuits significantly without increasing the circuit area.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.11
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• pp.20-25
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• 2016

This study addresses a low complexity and lossless frame memory compression algorithm based on block-buffer structure for efficient high resolution video processing. Our study utilizes the block-based MHT (modified Hadamard transform) for spatial decorrelation and AGR (adaptive Golomb-Rice) coding as an entropy encoding stage to achieve lossless image compression with low complexity and efficient hardware implementation. The MHT contains only adders and 1-bit shift operators. As a result of AGR not requiring additional memory space and memory access operations, AGR is effective for low complexity development. Comprehensive experiments and computational complexity analysis demonstrate that the proposed algorithm accomplishes superior compression performance relative to existing methods, and can be applied to hardware devices without image quality degradation as well as negligible modification of the existing codec structure. Moreover, the proposed method does not require the memory access operation, and thus it can reduce costs for hardware implementation and can be useful for processing high resolution video over Full HD.