• Title/Summary/Keyword: ATM switch

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A Study on Self-Load Balancing Mechanism for Improvement of Throughput in 640Gb/s ATM Switching system (640Gb/s ATM 스위칭 시스템의 Throughput 향상을 위한 Self-Load Balancing 메커니즘 연구)

  • Jang, Suk-Gi;Kim, Tae-Young;Kim, Hoon;Park, Kwang-Chae
    • Proceedings of the IEEK Conference
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    • 2001.06a
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    • pp.163-166
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    • 2001
  • Software controlled traffic management becomes more difficult with increasing switch size, because a huge number of connections are multiplexed in a high speed switching system and each ATM connections does not have a fixed bandwidth It is based on high-speed WDM(wavelength division multiplexed) links that can multiplex a huge number of connections on a statistical basis, and a self-load balancing technique. the Proposed switching system is scalable, and achieves the non-blocking capability without the use of complicated software control, using instead a hardware self-load balancing mechanism

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Congestion Control Scheme for Multimedia Traffic over ATM ABR Service

  • Kim, Jung-Youp;Lee, Sang-Heok;Park, Young-Bok
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.525-528
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    • 2000
  • According to the development of B-ISDN on ATM network, the uses of Multimedia service is growing. Although ABR service uses the network resource most effectively because it is able to change the transfer rate, it is not used for multimedia service until recently. In this paper, we set priority queue and non-priority queue in the ATM switch and each queue has threshold so is can be adopted in different transfer rate method. We propose the real-time traffic transfer method over ABR service based on an effective traffic control method.

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High Performance IP Fowarding Engine for ATM based Gigabit Routers

  • Park, Byeong-Cheol;Park, Chang-Sik;Jeong, Youn-Kwae;Lee, Jeong-Tae
    • Proceedings of the IEEK Conference
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    • 2000.07a
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    • pp.533-536
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    • 2000
  • In this paper, we proposed high performance packet forwarding engine for asynchronous transfer mode(ATM) based gigabit routers. The forwarding engine is based on ATM switch and accommodates four 622Mbps ports. The forwarding engine has been designed to be able to process the Intemet protocol(IP) packet at 2.5Gbps using the pipelined If header processing and lookup control mechanism. For high performance packet forwarding, we used content addressable memory(CAM) based routing coprocessor operating in hardware and implemented the pipelined lookup control function into a field programmable gate array(FPGA). The pipelined packet header processing mechanism enhanced the forwarding performance of the If packets ingressed from four different 622Mbps ports. Moreover, the If lookup controller designed to have the performance up to 12.5Mpps. The proposed forwarding engine is also designed to support differentiated services(DS) and multiprotocol label switching(MPLS).

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An Efficient TCP Congestion Control Scheme in ATM Networks (ATM 망에서 효율적인 TCP 폭주 제어 기법)

  • 최지현;김남희;김변곤;전용일;정경택;전병실
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.8
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    • pp.1653-1660
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    • 2003
  • In this paper, we proposed an enhanced TCP congestion control algorithm using RTT with congestion window parameter cwnd to minimize the effect of TCP congestion. The proposed scheme could avoid the occurrence of frequent congestion and decrease the delay caused by the recovery time and the using amount of switch buffer. Through the simulation, we showed that the proposed scheme cm acquire higher performance than the existing scheme. There are 22.56% improvement at the average using buffer efficiency, and packet drop rate is 0.1% which is less than existing scheme.

A Study on Implementation of a VC-Merge Capable Switch for QoS and Scalability on MPLS over ATM (ATM 기반 MPLS망에서 확장성과 QoS를 보장하는 VC-Merge 가능한 스위치 구현에 관한 연구)

  • Lee, Tae-Won;Kim, Young-Chul
    • Annual Conference of KIPS
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    • 2001.04a
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    • pp.541-544
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    • 2001
  • 본 논문에서는 ATM 기반 MPLS망에서 라우터의 레이블 공간을 효율적으로 사용하여 망의 확장성을 높이기 위한 방안인 레이블 통합 기능과 차등서비스를 지원하기 위하여 우선 순위 제어 알고리즘을 적용한 스위치 구조를 제안하고 이를 구현한다. 차등서비스(Differentiated Service)를 제공함에 있어서 레이블 통합 기능을 수행할 수 있는 적합한 구조를 제안하며, 망 폭주 발생 가능성이 있을 시 EPD(Early Packet Discard) 알고리즘을 통한 적응적 폭주 제어를 행함으로써 네트워크 자원의 낭비를 막고, VC-merge와 Non VC-merge 기법을 시뮬레이션을 통해 각각 비교 분석하였다. 또한 고속의 Switching을 위해 Input Queueing 방식과 Pipeline구조의 scheduler을 적용하였으며 제안한 스위치를 VHDL 모델링을 통하여 설계하고, 삼성 0.5um SOG 공정으로 칩을 제작한다.

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Predictive Traffic Control Scheme of ABR Service (ABR 서비스를 위한 예측 트래픽 제어모델)

  • 오창윤;임동주;배상현
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.4 no.2
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    • pp.307-312
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    • 2000
  • Asynchronous transfer mode(ATM) is flexible to support the various multimedia communication services such as data, voice, and image by applying asynchronous time-sharing and statistical multiplexing techniques to the existing data communication. ATM service is categorized to CBR, VBR, UBR, and ABR according to characteristics of the traffic and a required service qualities. Among them, ABR service guarantees a minimal bandwidth and can transmit cells at a maximum transmission rate within the available bandwidth. To minimize the cell losses in transmission and switching, a feedback information in ATM network is used to control the traffic. In this paper, predictive control algorithms are proposed for the feedback information. When the feedback information takes a long propagation delay to the backward nodes, ATM switch can experience a congestion situation from the queue length increases, and a high queue length fluctuations in time. The control algorithms proposed in this paper provides predictive control model using slop changes of the queue length function and previous data of the queue lengths. Simulation shows the effectiveness result of the proposed control algorithms.

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Design of a shared buffer memory switch with a linked-list architecture for ATM applications (Linked-list 구조를 갖는 ATM용 공통 버퍼형 메모리 스위치 설계)

  • 이명희;조경록
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.11
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    • pp.2850-2861
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    • 1996
  • This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.

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Proposal of optical subscriber access network using optical CDMA method with optical switches (광 스위치를 이용한 광 CDMA 방식에 의한 광 가입자 액세스 망의 제안)

  • Park, Sang-Jo;Kim, Bong-Kyu
    • The KIPS Transactions:PartC
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    • v.10C no.3
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    • pp.317-324
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    • 2003
  • In this paper, we propose the ATM based Passive Optical Network (PON) using the optical CDMA scheme with optical switches and PN codes in time domain. We also propose the bipolar optical receiving correlator for PN codes. As optical CDMA is performed by driving directly an optical switch on-off switching with PN codes, the number of distinct code sequences can be increased and the flexibility in assigning PN codes can be improved. Finally we theoretically analyze the signal-to-interference -plus-noise ratio and the bit error probability of regenerated signal and compare the performance of proposed scheme compared with ATM based PON using conventional optical CDMA with optical delay lines.

Dilated Banyan Network Recirculation (재순환 구조를 가진 dilated 반얀 네트웍)

    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.10B
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    • pp.1841-1851
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    • 1999
  • Banyan network has been widely employed as a basic building block for ATM switches. But the banyan network has very low routing capacity because of the internal blocking problem. Hence, a dilated banyan network has been used as one solution that can overcome the internal blocking problem. However, tremendous network capacity is wasted in the dilated network In this paper, we propose a dilated banyan network with deflection routing and recirculation mechanism to fully utilize the wasted capacity. The performance of the proposed switch is analysed under uniform traffic assumption. Numerical and simulation results show that the proposed switch yields a significant improvement of the maximum throughput as compared that of the pure dilated banyan network.

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