• Proceedings of the Korea Society for Industrial Systems Conference
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• 1997.11a
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• pp.147-161
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• 1997

In the future, the performance of B-lSDN offering the multimedia and a various service depends on the performance of switch that is the important factor consisting of network. Bufferless banyan network consisted of MIN(multistage interconnection network) selected for- the fabric of ATM switch and has a limitation of performance because of blocking. Input buffered banyan networks with FIFO(first-in first-out) buffering scheme for the reduction of blocking and the cell bypass queueing theory for the reduction of HOL(head of line) blocking were seperately compared of the performance of switch. Specially input buffered banyan networks were applied monotonic buffering scheme that was proposed. As a result of simulation, Buffered Banyan Network with cell bypass queueing theory showed better performance than FIFO type input buffered Banyan network. Monotonic increase buffering scheme showed better performance than Monotonic decrease buffering scheme.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.11
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• pp.25-33
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• 1997

The end-to-end rate-based control mechanism is used for the flow control of the ABR service to allow much more flexibility in ATM switching system. To accommodate the ABR service effciently many algorithms such as EFCI, EPRCA, ERICA, and CAPC2 have been proposed for the switch algorithm. ABR cells and related RM cells are received at the ATM switch fabric transparently without any processing. And then cells received from the traffic source are queued in the ABR buffer of switching system. The ABR buffer usually has some thresholds for easy congestion control signal transmission. Whatever we use, therefore, these can be many ABR traffic control algorithms to implement the ABR transfer capability. The genertion of congestion indicate signal for ABR control algorithms is determined by ABR buffer satus. And ABR buffer status is determined by ABR cells transfer ratio in ATM switch fabrics. In this paper, we presented the functional structures for control of the ABR traffic capability, proposed the readout scheduling, cell slot allocation of output link and the buffer allocation model for effective ABR traffic guranteeing with considering CBR/VBR traffics in ATM switch. Since the proposed readout scheduling scheme can provide more avaliable space to ABR buffer than existing readout scheduling scheme, generation rate of a SEND signal, that is, BCN signal in destination node can be increased for ABR call connection. Therefore, the proposed scheme, in this paper, can be appropriate as algorithm for effective ABR traffic service on output link of ATM switching node.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.311-315
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• 2008

The switching fabric used to make high speed switching for packet transfer between input and output interface in recent internet environments. Without making any changes in order to remain ATM switching fabric, the existing structures should split/reassemble a packet to certain size, set aside cross-point buffer and will put loads on the system. In this paper, we proposed a new switch architecture, which has separated data memory plane and switching plane packet data will be stored on the separate memory structure and simultaneously only the part of the memory address pointers can pass the switching fabric. The small mini packets which have address pointer and basic information would be passed through the switching fabric. It is possible to achieve the remarkable switching performance than other switch fabrics with contending variable length packets.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.383-386
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• 2001

This paper presents a novel multicast architecture for shared multibuffer ATM switch, which is tailored for throughput enhancement in multicast environments. The address queues for multicast cells are separated from those for unicast cells to arbitrate multicast cells independently from unicast cells. Three read cycles are carried out during each cell slot and multicast cells have chances to be read from shared buffer memory(SBM) in the third read cycle provided that the shared memory is not accessed to read a unicast cell. In this architecture, maximum two cells are queued at each fabric output port per time slot and output mask choose only one cell. Extensive simulations are carried out and it shows that the proposed architecture has enhanced throughput comparing with other multicast schemes in shared multibuffer switch architecture.

• Journal of Communications and Networks
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• v.17 no.3
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• pp.286-295
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• 2015

Avionic databuses fulfill a critical function in the connection and communication of aircraft components and functions such as flight-control, navigation, and monitoring. Ethernet-based avionic databuses have become the mainstream for large aircraft owning to their advantages of full-duplex communication with high bandwidth, low latency, low packet-loss, and low cost. As a new generation aviation network communication standard, avionics full-duplex switched ethernet (AFDX) adopted concepts from the telecom standard, asynchronous transfer mode (ATM). In this technology, the switches are the key devices influencing the overall performance. This paper reviews the avionic databus with emphasis on the switch architecture classifications. Based on a comparison, analysis, and discussion of the different switch architectures, we propose a new avionic switch design based on a time-division switch fabric for high flexibility and scalability. This also merges the design concept of space-partition switch fabric to achieve reliability and predictability. The new switch architecture, called space partitioned shared memory switch (SPSMS), isolates the memory space for each output port. This can reduce the competition for resources and avoid conflicts, decrease the packet forwarding latency through the switch, and reduce the packet loss rate. A simulation of the architecture with optimized network engineering tools (OPNET) confirms the efficiency and significant performance improvement over a classic shared memory switch, in terms of overall packet latency, queuing delay, and queue size.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.463-470
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• 2003

Many types of switching fabrics have been proposed for use in ATM networks. Multistage Interconnection Networks (MINs) constitute a large class of ATM switching systems that are widely used in today´s internetworking. One of the most veil-known types of multistage networks is the banyan network. The banyan network is attractive for its simple routing scheme and low hardware complexity, but its throughput is very limited due to internal blocking and output contention. In this paper, we propose an input-buffered dual-banyan switch model with multiple switching fabric between switch input and output to avoid internal and Head-of Line blocking. By performance analysis and simulation, we show that our model has a lower ceil delay and 96% throughput which is much better than other banyan-type switch architecture.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1581-1589
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• 1999

In B-ISDN(Broadband Integrated Services Digital Networks), the efficient implementation of multicast function is very important since the demand for distributed type of service such as VOD(Video On Demand) system is expected to grow. In this paper, the multicast performance characteristics of fully-interconnected switch fabric used for our research is the proper architecture for a small-sized switch element, and it uses bit addressing method for addressing scheme and thus it is easy to implement multicast function without adding a function block. To incorporate the bursty nature of traffic in ATM networks, we used IBP(Interrupted Bernoulli Process) model as an input traffic model. We presented and analyzed the simulation results in terms of the multicast operation of the switch. Based. on this study, it its analyzed that congestion avoidance may be feasible if we use a proper traffic control scheme by finding an overload point due to multicast.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.264-267
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• 2002

This paper presents the design of a pipelined virtual output queue routing engine for an advanced input-queued ATM switch, which has a serial cross bar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array (FPGA) chip with a 77MHz operating frequency, 16$\times$16 switch size, and 2.5Gbps/port speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.394-397
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• 2003

In this paper, we describe the implementation of high performance buffer manager that is used in an advanced input-queued switch fabric. The designed buffer manager provides wire-speed cell/packet routing with low cost and tolerates the transmission pipeline latency of request and grant data. The buffer manager is implemented in a FPGA chip and supports the speed of OC-48c, 2.5Gbps per port.

• The KIPS Transactions:PartC
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• v.12C no.1 s.97
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• pp.83-96
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• 2005

The multichannel switch is an architecture widely used for ATM (Asynchronous Transfer Mode). It is known that the fault tolerant characteristic can be incorporated into the multichannel crossbar switching fabric. For example, if a link belonging to a multichannel group fails, the remaining links can assume responsibility for some of the traffic on the failed link. On the other hand, if a fault occurs in a switching element, it can lead to erroneous routing and sequencing in the multichannel switch. We investigate several fault localization algorithm in multichannel crossbar ATM switches with a view to early fault recovery. The optimal algorithm gives the best performance in terms of time to localization but it is computationally complex which makes it difficult to implement. We develop an on-line algorithm which is computationally more efficient than the optimal one. We evaluate its performance through simulation. The simulation results show that the Performance of the on-line algorithm is only slightly sub-optimal for both random and bursty traffic. There are cases where the proposed on-line algorithm cannot pinpoint down to a single fault. We enumerate those cases and investigate the causes. Finally, a fault recovery algorithm is described which utilizes the information provided by the fault localization algorithm The fault recovery algorithm providesadditionalrowsandcolumnstoallowcellstodetourthefaultyelement.