• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.1926-1940
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• 1998

This paper is the part II of research results on the performance evaluation of fully interconnected ATM switch, and includes the performance evaluation results for bursty traffic and nonuniform distribution. The switch model is a fyully interconnected switch type proposed by ETRI and is the proper architecutre for a small-sized switch element. The proposed switch consists of two steps of buffering scheme in the switch fabric in order to effectively absorb the effect of bursty nature of ATM traffic. The switch uses bit addressing method for addressing shcmeme and thus it is easy to implement multicasting function without adding additional functional block. In order to incorporate the bursty nature of traffic in ATM networks, we use IBP(Interrupted Bernoulli Process) model as an input traffic model as well as random traffic model which has been used as a traditional traffic model. In order to design the various scenarios for simulation, we considered both uniform and nonuniform output distribution, and also implemented multicast function. In this paper, we presented the simulation results in diverse environments and evaluated the performance of the switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1148-1159
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• 1997

In the broadband integrated service digital networks (B-ISDN), ATM switches hould be abld to accommodate diverse types of applications ith different traffic characteristics and quality ddo services (QOS). Thus, in order to increase the utilization of switches and satisfy the QOS's of each traffic type, some types of priority control schemes are needed in ATM switches. In this paper, a nonblocking input and output queueing ATm switch with capacity C is considered in which two classes of traffics with different loss probability constraints are admitted. 'Partial push-out' algorithm is suggested as a loss priority control schemes, and the performance of this algorithm is analyzed when this is adopted in input buffers of the switch. The quque length distribution of input buffers and loss probabilities of each traffic are obtained using a matrix-geometric solution method. Numerical analysis and simulation indicate that the utilization of the switch with partial push-out algorithm satisfying the QOS's of each traffic is much higher than that of the switch without control. Also, the required buffer size is reduced while satisfying the same QOS's.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.80-90
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• 1996

The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10b
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• pp.1533-1536
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• 2001

This paper considers the TMN system for management of public ATM switching network which has the four-level hierarchical structure consisting of one network management system, a few element management system and several agent-ATM switch pairs, respectively. The effects of one TMN command on the local call processing performance of the component ATM switch an analyzed using Jackson's queueing model. The TMN command considered is the permanent virtual call connection, and the performance measures of ATM switch are the utilization, mean queue length and mean waiting time for the processor interfacing the subscriber lines and trunks directly, and the call setup delay of the ATM switch.

• Journal of the Korea Society for Simulation
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• v.8 no.1
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• pp.51-61
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• 1999

A cell scheduling method of Queue for the ATM switch is proposed and simulated. In this paper, we present the cell scheduling method proper to the proposed queue and the improved queue with Queue Sharing(QS) structure for CBR, VBR, ABR traffic. The proposed QS structure minimizes the CLS(Cell Loss Ratio) of ABR traffic and decreases the CLR of bursty VBR traffic. Also we propose a cell scheduling method using VRR(Variable Round Robin) scheme proper to the high-speed(ATM) switch. The VRR scheme provides a fairness in terms of service chance for the queues in the ATM switch as well as QOS of their cell delay characteristic of CBR and VBR traffic, QOS of ABR CLR. The simulation results show the proposed method achieves excellent CLR and average cell delay performance for the various ATM traffic services in the Queue Sharing structure.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.433-437
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• 2000

We fabricated switch module of ATM(Asynchronous Transfer Mode) exchange system with MCM-C(MultiChip Module Co-fired) technology and measured its electrical characteristics. Green tape was used as substrate and Au/Ag paste was used to form the interconnect layers. The via holes were made by drill and filled with metal paste usign screen method. After manufacturing the substrate, chips and passive components were assembled on the substrate. In electrical test, the module showed the output signal of 46.9MHz synchronized with input signal. In the view of substrate size reduction, the area of MCM switch module was 35% of conventional hybrid switch module.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.9
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• pp.24-29
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• 2000

As a result of the continuing increase in the high capacity and high speed requirement, ATM will be important technology. But previous AAL type cant support service that is variable length, low speed. So AAL2 is the most recently standardized AAL type, which is aimed at providing for the bandwidth efficient transmission of low-rate, short, and variable length packets in delay-sensitive applications. In this paper, we propose the architecture and the behavior of scalable AAL2 switch that are far different from ATM switch. Also, the performance of the designed switch is analyzed by computer simulation.

• The KIPS Transactions:PartC
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• v.10C no.4
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• pp.485-492
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• 2003

This paper presents a new modified input buffered switch, which called a grouped input buffered (GIB) switch, to eliminate the influence of HOL blocking when using multiple input buffers in ATM switches. The GIB switch consists of grouped sub switches per a network stage. The switch gives extra paths and buffered switching elements between groups for transferring the blocked cells. As the result, the proposed model can reduce the effect by the HOL blocking and thereafter it enhances the performance of the switch. The simulation results show that the proposed scheme has good performance in comparison with previous works by using the parameters such as throughput, cell loss, delay and system power.

• ETRI Journal
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• v.19 no.4
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• pp.326-343
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• 1997

In this paper, we propose an ATM switch with the rate more than gigabits per second to cope with future broadband service environments. The basic idea is to separate the connection control flow from the data information flow inside the switch. The proposed switch has a dual-plane switch matrix with the synchronous control algorithm. The queuing behaviors of the proposed switch are shown by the discrete-time queuing analysis. Numerical analyses are taken both in the non-blocking crossbar switch and the banyan switch with internal blocking. Results show that a proposed dual-plane $16{\times}16$ switch would have the acceptable performance with maximum throughput of about 95 percent.

• Management Science and Financial Engineering
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• v.10 no.2
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• pp.89-102
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• 2004

In this paper, we deal with a processor assignment problem that minimizes the total traffic load of an ATM switch controller by optimally assigning processors to ATM interface units. We develop an integer programming (IP) model for the problem, and devise an effective tabu search heuristic. Computational results reveal the efficacy of the proposed tabu search procedure, finding a good quality solution within 5% of optimality gap.