• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1131-1132
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• 2008

In this paper, we developed UHF RFID R/W system using AT91SAM7S256(ARM chip), UHF RFID R/W module (WJ7090) and wireless LAN(IEEE 802.11.a/b). And we developed a transmission/receiving packet which is send to UHF R/W module in AT91SAM7S256. In order to show the usefulness of UHF RFID R/W system, we executed a performance test. The developed UHF RFID R/W system shows better performance for reading of RFID tag and data transmission through wireless LAN.

• Journal of Information Processing Systems
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• v.3 no.1
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• pp.16-20
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• 2007

This paper describes the development of the sensor interface and driver program for a point of care (POC) device. The proposed pac device comprises an ARM9 embedded processor and eight-channel sensor input to measure various bio-signals. It features a user-friendly interface using a full-color TFT-LCD and touch-screen, and a bluetooth wireless communication module. The proposed device is based on the system on a programmable chip (SOPC). We use Altera's Excalibur device, which has an ARM9 and FPGA area on a chip, as a test bed for the development of interface hardware and driver software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.69-77
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• 2002

In this paper, we present the CDMA2000 1x compliant mobile station modem chip (SCom5010) implemented in a 0.18${\mu}{\textrm}{m}$ CMOS technology.[1] ARM940T cached processor. TeakLite DSP core, and other peripheral blocks are integrated with the baseband modem chip. Also we show novel verification methodologies and explain how this chip can be used as an emulation processor.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.416-420
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• 1999

This paper describes a 32-bit RISC processor, which has instruction level compatibility with the ARM7 microprocessor. The processor is fully synthesizable, and its performance is evaluated based on 0.35-${\mu}{\textrm}{m}$ CMOS library. This paper focuses on the implementation of the processor and the reliable verification strategy ensuring the complete instruction level compatibility. The processor has successfully verified using a FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Journal of the Korean Institute of Intelligent Systems
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• v.16 no.5
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• pp.556-561
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• 2006

It is very important to classify the DNA Chip image pattern in order to acquire useful information about genetic disease of people. In this paper, we developed the novel pattern classification method of DNA Chip image using MLP based back-propagation and Self organizing Map learning algorithm. And then we compared and analyzed these classified pattern results. Also we carried out experiment in the MV2440 board using CPU Cote for S3C2440(ARM 920T) and PC environment, and displayed its results in order to give the genetic information to user mote easily in various environment.

• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.1
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• pp.19-24
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• 2008

To reduce time-to-market, more and more embedded system developers and system-on-chip designers rely on microprocessor-based design methodology. ARM processor has been a major player in this industry over the last 10 years. However, there are many restrictions on developing embedded software using ARM processor in the early design stage. For those who are not familiar with embedded software development environment or who cannot afford to have an expensive embedded hardware equipment, testing their software on a real ARM hardware platform is a challenging job. To overcome such a problem, we have designed VMA (Virtual ARM Machine), which offers easier testing and debugging environment to ARM based embedded system developers. Major benefits that can be achieved by utilizing a virtual ARM platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. Unlike many other purely software-oriented ARM simulators which are independent of real hardware platforms, VMA is specifically targeted on SYS-Lab 5000 ARM hardware platform, (designed by Libertron, Inc.), which means that VMA imitates behaviors of embedded software as if the software is running on the target embedded hardware as closely as possible. This paper will describe how VMA is designed and how VMA can be used to reduce design time and cost.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.185-191
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• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1717-1722
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• 2003

In this paper we developed flip-chip bonder using XY stage, liner-rotary actuator and vision system. We depicted the major parts of the developed flip-chip bonder. Then we discussed several problems and their solutions such as vision and motion control, pick-up module position accuracy, separation of chip from the blue taped hoop, etc. We used a post guide to improve the horizontal positional accuracy against the long arm. Also, we used an ejector module and synchronization technique for easy chip separation from the blue tape.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.410-415
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• 2002

This paper describes the implementation of a SoC(System-on-a-Chip) and an ISDN communication terminal by the SoC in ISDN network. The SoC has been developed with the functions of 32-bit ARM7TDMI RISC core processor, network connection with S/T interface, TDM--bus interface and voice codec, user interface. And we also review the developed software structure and the ISDN service protocol procedures which are working on the SoC. And finally this paper describers a structure of an ISDN terminal equipment using the implemented SoC and terminal software.