• Journal of KIISE
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• v.42 no.5
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• pp.551-557
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• 2015

The technology using ARM TrustZone draws attention as a new embedded virtualization approach. The ARM TrustZone defines two virtual execution environment, the secure world and the normal world. In such an environment, the inter-world communication is important to extend function of software. However, the current monitor software does not sufficiently support the inter-world communication. This paper presents a new inter guestOS communication scheme, for each world, for the ARM TrustZone virtualization. The proposed communication scheme supports bidirectional inter-world communication for single core and multicore environment. In this paper, It is implemented on a NVIDIA Tegra3 processor based on the ARM Cortex-A9 MPCore and it showed a bandwidth of 30MB/s.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1165-1168
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• 2004

본 논문은 임베디드 장비에 사용되는 코어중 시장의 약 70% 이상을 점유하고 있는 ARM(Advanced RISC Machine) 코어에서의 BOF(Buffer OverFlow)에 대해서 논하고자 한다. 먼저, ARM 아키텍처에서 함수 호출시 스택의 변화에 대해서 기술하고 이 환경에서 시스템 공격 기법 중 가장 빈번한 BOF가 어떻게 이루어지는가에 대해서 설명한다. 그리고 ARM 아키텍처만이 가지는 특징을 이용하여 이에 대처하는 방법을 제안 한다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.457-459
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• 2000

최근 이동단말기나 PDA, 스마트폰과 같은 정보기기나 디지털 가전기기의 사용이 증대됨에 따라, ARM코어 시스템을 기반으로 하는 프로세서와 이를 운영하기 위한 소프트웨어 수요도 증가하고 있다. 본 논문은 프로세서를 운영하기 위한 소프트웨어 중에서 예외처리를 위한 일반적인 인터럽트 제어를 다룬다. ARM 시스템 상에서 임의의 주변 장치(타이머/카운터)에 의해 발생하는 인터럽트 처리 과정과 예외처리를 제어하기 위한 벡터 테이블을 구성하는 방법에 대해 분석한다. 그리고 인터럽트를 처리하는 인터럽트 코드부분과 벡터 테이블내의 인터럽트의 상호 연관성에 대해 논의한다.

• Journal of KIISE
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• v.43 no.9
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• pp.1060-1065
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• 2016

Recently, there is an emerging need for parallel UHD video processing, and the usage of computing systems that have an asymmetric processor such as ARM big.LITTLE is actively increasing. Thus, a new parallel UHD video processing method that is optimized for the asymmetric multicore systems is needed. This paper proposes a novel HEVC tile partitioning method for parallel processing by analyzing the computational power of asymmetric multicores. The proposed method analyzes (1) the computing power of asymmetric multicores and (2) the regression model of computational complexity per video resolution. Finally, the model (3) determines the optimal HEVC tile resolution for each core and partitions/allocates the tiles to suitable cores. The proposed method minimizes the gap in the decoding time between the fastest CPU core and the slowest CPU core. Experimental results with the 4K UHD official test sequences show average 20% improvement in the decoding speedup on the ARM asymmetric multicore system.

• Journal of Internet Computing and Services
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• v.11 no.4
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• pp.95-106
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• 2010

Recently multiple process communicate together. They share resource and information for cooperation in complicated programming environment. Kernel provides IPC (Inter -Process Communication) for communication with each other process. Shared Memory is a technique that many processes can access to identical memory area in the Linux environment. In this paper, we propose a performance improvement method of shared memory in the dual-core embedded linux system which is consist of different core and different operating system. We construct the MPC2530F (ARM926F+ARM946E) linux system and measure the performance therein. We attempt a performance enhancement in each CPU for each process which uses a shared memory.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.6
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• pp.82-92
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• 2001

This paper describes implementation of an embedded 32-Bit RISC core for portable communication/information equipment, such as cellular phones, PDA(Personal Digital Assistants), notebook, etc. The RISC core implements the ARM$\circled$V 4 instruction set, operates with typical 5-stage pipeline. It supports Thumb code to improve the code density, and uses the dynamic power management method of pipeline registers. It was modeled and simulated in RTL level using VHDL, and verified with ARMulator of ADS (Arm Developer Suite) and had average CPI of 1.44. The core is synthesized automatically using the cell library based on $0.6{\mu}m$ CMOS 1-poly 3-metal CMOS technology. It consists of about 41,000 gates and the clock frequency is expected to be above 45 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1412-1420
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• 1999

In order to enhance multi-channel audio signals, Dolby Pro Logic is widely used especially for the Hi-Fi audio system, since it can provide highly stereophonic effects and a nice separation of multi-channel sound. This paper describes an implementation of Dolby Pro Logic decoder with ARM-7 core. The code is modified for the fixed point operation and optimized. For the verification of the code, the operation time and the precision are estimated thoroughly. As a result, it is verified that Dolby Pro Logic decoder can be implemented with ARM-7 core operating at 54 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1042-1050
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• 2007

This paper describes the system which automatically generates power-minimized embedded cores from MDL descriptions. An automatic generation system is constructed which generated embedded cores which consumes less power for application programs. From the usage information on pipeline stages for each instruction, the proposed system generates embedded cores with the capability of detecting/resolving pipeline hazards. The generated cores are configured such that the power consumption is minimized. The proposed system has been tested by generating HDL codes for ARM9, MIPS R3000 architectures. Experimental results show functional accuracy of the generated cores, and show that power reduction of $20%{\sim}40%$ has been observed for benchmark programs.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1281-1284
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• 2002

본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32 비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 톤 발생 및 음성신호 접속기능과 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.04a
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• pp.466-468
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• 2000

ARM 프로세서는 CISC 보다는 간단하게 디자인된 RISC로서 내장 응용프로그램에 적합하기 때문에 앞으로 모든 디지털 기기에 ARM 코어를 기반으로 한 핵심 칩들이 생산된다. 그러나 명령어가 CISC보다는 적기 때문에 주어진 작업에 대해 완전한 처리를 위해서는 보다 많은 명령어들을 필요로 한다. 이러한 ARM 프로세서에서 데이터를 전송할 때 사용하는 메모리 영역과 레지스터들을 프로그램과 함께 분석하였다.