• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.317-320
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• 2002

Recently, AMBA(Advanced Microcontroller Bus Architecture) is used as common system bus at embedded system. In this paper, we described test method of peripheral device which is connected to AMBA according to the bus interface defined by AMBA protocol We implemented one of the APB(Advanced Peripheral Bus) peipheral module, GPIO(General Purpose Input/output), and tested its functionality as il is connected to the AMBA system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.126-133
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• 2006

This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.74-79
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• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.44-54
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• 2011

The goal of this paper is reducing the test time for AMBA-based SoC. To achieve this goal, the design technique that can test several cores concurrently by reusing AMBA as TAM is proposed. The additional control logic for structural parallel core test is minimized by reusing TIC which is originally used for functional test of AMBA. SoC reliability and test time reduction can be significantly achieved with the concurrent core test technique as well as functional test.

• The Journal of the Korea Contents Association
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• v.4 no.4
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• pp.179-187
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• 2004

In this paper, we have designed an LCD controller based on AMBA. Normally display systems using the LCD are adopted independent bus architecture for high speed data access. Proposed LCD controller complies with AMBA data format and has an image scaler that executes interpolation for full screen display. This image scaler employs FOI for horizontal scaling and H-Shape pseudomedian filter for vertical scaling. It has been designed with VHDL and verified on prototype board using Xilinx FPGA and LCD panel.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.658-660
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• 2003

본 논문에서는 AMBA 기반의 FPD 시스템에 적용 가능한 콘트라스트 컨트롤러를 설계 및 구현하였다. 제안한 콘트라스트 컨트롤러 내부에는 AMBA의 인터페이스 spec을 준수한 AMBA AHB 컨트롤러와 콘트라스트조정 블록, 메모리 컨트롤러. FPD 컨트롤러가 내장되어있다. 구현한 알고리즘은 실시간 처리가 가능하며 콘트라스트의 범위를 조정하는 가중치를 가진 알고리즘으로 기준되는 값을 이용하여 콘트라스트의 효율적인 조정이 가능하다. 콘트라스트 컨트롤러는 VHDL로 설계하였으며 FPGA를 이용한 H/W를 구현하여 TFT-LCD panel에 디스플레이 하여 검증하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.554-561
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• 2006

In recent years, as SoC design research is actively conducted, a large number of IPs are included in a system. Various bus protocols and bus architectures are designed to increase IP reusability. Among them, the AMBA AHB became a de facto standard although it is somewhat inadequate for a large scale SoC. We proposed SNP and SNA, high performance on-chip-bus protocol and architecture, respectively, to solve the problem of the conventional shared buses. However, it seems to be imperative that the new on-chip-bus system support AMBA-compatible IPs for a while since there are a lot of IPs with AMBA interface. In this paper, we propose an extended SNP specification and a corresponding SNA component to support ABMA-compatible IPs used in SNA - based system. We extend the phase of the SNP by 1 bit to add new 8 phases to support communication based on AMBA protocol without penalty of elongated cycle latency. The ARB-to -XSNP converter translates the protocol between AHB and SNP to attach AMBA -compatible IPs to SNA based system. We show that AMBA IPs can communicate through SNP without any degradation of performance using the extended SNP and AHB - to- XSNP converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.390-398
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• 2004

This paper describes a study on the automatic generation system of the interface for communication among AMBA bus and IPs with different protocols. Employing an extended STG, the proposed system generates the interface modules required for the communication among IPs with different protocols. For an example system, the interface module for communication between AMBA AHB bus and a video decoder has been generated and verified in its functionality. The area and latency have been compared with the manually designed interface. For burst-mode communication, the generated interface module shows the comparable performance with the manually designed module. For single-mode communication, the generated interface module shows a slightly worse performance than the manually designed module. However, the increased area is negligible considering the size of the IP.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.712-713
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• 2011

In this paper, the AMBA AXI slave unit that can verify the pipelined arithmetic unit is proposed and the 2-stage 16-bit pipelined multiplier is introduced as design example. The proposed AXI slave unit consists of input buffer block memory, control registers, pipelined arithmetic unit, control unit, output buffer block memory, and AXI slave interface unit. The main operational procedures are divided into the following steps, such as burst-mode input data loading for the input buffer memory, programming of control registers, arithmetic operations for block data in the input buffer memory, and burst-mode output data unloading from output buffer memory to host processor. Because the proposed AXI slave unit is general structure, it can be efficiently applicable to AMBA AXI and AHB slave unit with pipelined arithmetic unit.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.735-738
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• 2005

This paper presents an AMBA-based IP that can perform the deblocking filtering operations required in the H.264 video compression. The deblocking filter circuit was optimized for area and performance. The AHB wrapper was added to the circuit to interface with the AMBA-based platform. The AMBA-compliant operation of the proposed IP was verified on the platform board with Xilinx Virtex2 XC2V600 FPGA and ARM9 processor.