• Proceedings of the Korean Society for Bioinformatics Conference
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• 2004.11a
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• pp.77-85
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• 2004

A significant portion (about 8% in human genome) of mammalian mRNA sequences contains AU(Adenine and Uracil) rich elements or AREs at their 3' untranslated regions (UTR). These mRNA sequences are usually stable. ARE motifs are assorted into three classes. The importance of AREs in biology is that they make certain mRNA unstable. We analyzed the occurrences of AREs and Alu, and propose a possible mechanism on how human mRNA could acquire and keep A REs at its 3' UTR originated from Alu repeats. Interspersed in the human genome, Alu repeats occupy 5% of the 3' UTR of mRNA sequences. Alu has poly-adenine (poly-A) regions at the end that lead to poly -thymine (poly-T) regions at the end of its complementary Alu. It has been discovered that AREs are present at the poly -T regions. In the all ARE's classes, 27-40% of ARE repeats were found in the poly -T region of Alu with mismatch allowed within 10% of ARE's length from the 3' UTRs of the NCBI's reference m RNA sequence database. We report that Alu, which has been reported as a junk DNA element, is a source of AREs. We found that one third of AREs were derived from the poly -T regions of the complementary Alu.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.229-232
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• 2009

In this paper, we propose a new programmable shader architecture based on an effective ALU operation. Today's mobile devices need the programmable shader processor for a three-dimensional(3D) graphics. The programmable shader processors require a lager ALU than a fixed pipeline ALU used previously. The proposed ALU architecture is able to execute two different arithmetic operations at the same time. Two instructions which need exclusive ALU operations are inserted into instruction decoders in parallel. Experimental results show the number of instruction cycles can be substantially reduced up to 40%.

• Progress in Superconductivity
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• v.5 no.1
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• pp.21-25
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• 2003

We have designed and simulated an 1-bit ALU (Arithmetic Logic Unit) by using a half adder. An ALU is the part of a computer processor that carries out arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We constructed an 1-bit ALU by using only one half adder and three control switches. We designed the control switches in two ways, dc switch and NDRO (Non Destructive Read Out) switch. We used dc switches because they were simple to use. NDRO pulse switches were used because they can be easily controlled by control signals of SET and RESET and show fast response time. The simulation results showed that designed circuits operate correctly and the circuit minimum margins were ＋/-27%. In this work, we used simulation tools of XIC and WRSPICE. The circuit layouts were also performed. The circuits are being fabricated.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.28B no.7
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• pp.520-534
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• 1991

This paper describes the design of an ALU and a shifter for RISC. The RISC datapath is designed to have a 4-stage pipeline and a 20 MHz operating frequency. The ALU makes use of the 32-bit BLC adder which has the characteristics of high speed ane regular structuer and executes the arithmetic instructions-addition and subtraction- and the logical instructions-AND, OR, and XOR. Additionally, multiplication is possible by iterative executions of step instructions to perform shift and add operations. The shifter is implemented by using the modified of funnel shifter. The shifter is able to perform the arithmetic andlogical shift instructions without maskiog. Moreover, it carries out data align operation which conforms to big endian byte address. The logical operation of the desinged ALU and the shifter were simulated using YSLOG and VLSIsim. SPICE simulation results using 1.2um double metal process parameters show that the ALU and shifter have a delay time of 15.9NS and 9.9NS, respectively. Therefore, the ALU and the shifter operates correctly above 20[ MHz ] click ferquency and are composed of about 7K and 15K teansistors, respectively.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1169-1172
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• 1998

We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.

• Microbiology and Biotechnology Letters
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• v.49 no.3
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• pp.316-319
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• 2021

Restriction endonucleases play an important role in molecular cloning, clinical diagnosis, and pharmacological drug studies. In this study, DNA-templated copper nanoclusters (DNA-CuNCs) were used to detect AluI endonuclease activity due to their high fluorescence emission and rapid synthesis of DNA-CuNCs under ambient conditions. Results showed that AluI activity was detected in a highly sensitive manner at low concentrations of AluI endonuclease by the fluorescence intensity of DNA-CuNCs. Additionally, its inhibition was monitored in the presence of daidzein under optimal conditions.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.59-65
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• 2013

Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.123.2-123.2
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• 2011

$ALU^+$ 태양전지는 PN접합을 후면에서 즉, Al을 소성하여 형성시키기 때문에 얼마나 균일하고 두껍게 형성하는 것이 가장 중요하다. 소성(Firing)은 태양전지 제조 과정에서 후면의 접촉을 위한 중요한 공정이다. 본 연구에서는 상업화가 가능한 n-type $ALU^+$ Emitter 태양전지에서 소성 횟수에 따른 특성을 연구 하였다. $ALU^+$ emitter 형성의 최적화를 위해 소성온도를 가변하고, 최적화된 온도에서 소성 횟수에 따른 DIV 측정을 통해 셀을 분석 하였다. 소성 횟수는 1~3회로 하였고, 그 결과 단락전류 밀도(Jsc)가 33.57mA/$cm^2$로 처음보다 15.1%증가 하였고, 곡선인자(Fill Factor)는 3회에서 66.04%로 218%증가 하였다. Al을 짧은 시간 안에 소성을 시키므로 해서 후면의 $P^+$ Emitter가 균일하게 형성되었기 때문에 개방전압(Voc)의 증가를 확인하였다. 본 연구를 통해 $ALU^+$ 태양전지의 후면 Aluminium 소성 조건의 최적화를 통하여 $ALU^+$ emitter가 충분히 형성되지 못하면 누설전류가 발생되고 직렬저항(Rs)이 크게 증가하여 개방전압(Voc) 및 단락전류밀도(Jsc)의 감소가 발생하게 되고, 직렬저항(Rs)의 증가와 병렬저항(Rsh)의 감소는 Fill Factor의 급격한 감소를 초래하게 됨을 알 수 있다. 이를 개선하면 태양전지 효율을 상승시키는 결과를 얻을 수 있음을 확인하였다.

• Progress in Superconductivity
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• v.6 no.2
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.