• Title/Summary/Keyword: ALU

Search Result 205, Processing Time 0.028 seconds

The Design of High Speed Processor for a Sequence Logic Control using FPGA (FPGA를 이용한 시퀀스 로직 제어용 고속 프로세서 설계)

  • Yang, Oh
    • The Transactions of the Korean Institute of Electrical Engineers A
    • /
    • v.48 no.12
    • /
    • pp.1554-1563
    • /
    • 1999
  • This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

  • PDF

The Relative Identification of C. officinale and L. chuanxiong by PCR-Mediated Fingerprinting (천궁류(川芎類) 한약재의 유전자 감식 연구)

  • Choi, Ho-Young;Kim, Dong-Wook;Kim, Dong-Eun;Suh, Young-Bae;Ham, In-Hye
    • The Korea Journal of Herbology
    • /
    • v.20 no.4
    • /
    • pp.151-161
    • /
    • 2005
  • Objectives : Our research purpose is to establish the standard identification analysis on C. officinale and L. chuanxiong in Korea and China by PCR-mediated fingerprinting. Methods : The Restriction Fragment Length Polymorphism (RFLP) and Randomly Amplified Polymorphic DNA (RAPD) method was used on Internal Transcribed Spacer (ITS) regions and rbcL regions to compare and discriminate genes extracted from crude drugs as C. officinale and L. chuanxiong in Korea and China. Results : L. chuanxiong Korea and China have very similar polymorphism, whereas L. chuanxiong in Korea and C. officinale have very different polymorphism in RFLP. And restriction enzymes AluI and SacI forms the specific fragment band only in C. officinale, they can be used as RFLP marker on ITS regions to discriminate among the species. Conclusions : The results could be applied in discriminating crude drugs among C. officinale and L. chuanxiong in Korea and China. Also they could be used in controlling drug quality, preserving medicinal plants, and improving plant description.

  • PDF

Mixed Infection of 16S rDNA I and V Groups of Phytoplasma in a Single Jujube Tree

  • Lee, Sang-Hun;Han, Sang-Sub;Cha, Byeong-Jin
    • The Plant Pathology Journal
    • /
    • v.25 no.1
    • /
    • pp.21-25
    • /
    • 2009
  • Jujube trees infected with phytoplasma exhibit symptoms of typical witches' broom, such as yellowing, abnormally small leaves, short internodes and proliferation of shoots. A 1.2 kb fragment of the 16S rDNA from jujube phytoplasma was generated by R16F2n/R16R2 primer pair from earlier amplified P1/P7 PCR products of cloned jujube witches' broom phytoplasmas. Enzymatic restriction fragment length polymorphism (RFLP) and sequence analysis of 16S rDNA revealed that the jujube tree was infected with 16S rDNA I and V groups of phytoplasmas. Extensive comparative analyses of restriction enzyme profiles from Alu I, Hha I, Msp I, and Rsa I clearly classified the two into different phytoplasma groups. The phylogenie analyses based on 16S rDNA showed that the similarity of the two different clones was 87.5%. This is the first report of a mixed phytoplasmal infection in a single jujube tree.

Design and Measurement of an SFQ OR gate composed of a D Flip-Flop and a Confluence Buffer (D Flip-Flop과 Confluence Buffer로 구성된 단자속 양자 OR gate의 설계와 측정)

  • 정구락;박종혁;임해용;장영록;강준희;한택상
    • Progress in Superconductivity
    • /
    • v.4 no.2
    • /
    • pp.127-131
    • /
    • 2003
  • We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

  • PDF

Design and Measurement of SFQ DFFC and Inverter (단자속 양자 DFFC와 Inverter의 설계와 측정)

  • 정구락;홍희송;박종혁;임해용;강준희;한택상
    • Progress in Superconductivity
    • /
    • v.5 no.1
    • /
    • pp.17-20
    • /
    • 2003
  • We have designed and measured a SFQ(Single Flux Quantum) DFFC and an Inverter(NOT) for superconducting ALU(Arithmetic Logic Unit) development. To optimize the circuit, we used Julia, XIC, and L meter for circuit simulations and circuit layouts. The Inverter was consisted of a D Flip-Flop, a data input, a clock input and a data output. If a data pulse arrives at the inverter, then the output reads ‘0’ (no output pulse is produced) at the next clock period. If there is no input data pulse, it reads out ‘1’(output pulse is produced). The DFFC was consisted of a D flip-Flop, an Inverter, a Data in, a Clock in and two outputs. If a data pulse arrives at the DFFC circuit, then the output2 reads ‘1’ at the next clock period, otherwise it reads out ‘1’ to output1. Operation of the fabricated chip was performed at the liquid helium temperature and at the frequencies of 1KHz.

  • PDF

A Simple PCR-RFLP for Idenficiation of Bursaphelenchus spp. Collected from Korea

  • Han, Hye-Rim;Han, Bo-Young;Chung, Yeong-Jin;Shin, Sang-Chul
    • The Plant Pathology Journal
    • /
    • v.24 no.2
    • /
    • pp.159-163
    • /
    • 2008
  • Accurate identification of pine wood nematode, Bursaphelenchus xylophilus is a prerequisite to diagnose the pine wilt disease. However, a fungivorous nematode, B. mucronatus is highly similar to B. xylophilus and it is difficult to differentiate these two species by morphological features. A molecular diagnosis method, ITSRFLP was applied for the identification of B. xylophilus and B. mucronatus from Korea. Genomic DNA was extracted from a single individual nematode and ITS DNA was amplified by PCR. The size of PCR product was approximately 900bp and the sequence data were obtained after cloning. Amplified ITS was digested by 5 different restriction enzymes (Rsa I, Hae III, Msp I, Hinf I, and Alu I) and provided a discriminatory profile for B. xylophilus and B. mucronatus. Besides, B. mucro- natus was determined to have 2 different genotypes, East Asian type and European type also clearly separated by Rsa I and Hae III digestion. European type of B. mucronatus is recently collected from Pinus koraiensis and has not been reported before. ITS sequnce data were analyzed by Restriction Mapper program and the result supported ITS-RFLP pattern. These data indicated that PCRRFLP method is an accurate and simple way for identification of Bursaphelenchus species.

Genetic Relationships of Cattle Breeds Assessed by PCR-RFLP of the Bovine Mitochondrial DNA D-loop Region

  • Yoon, Du Hak;Lee, Hak Kyo;Oh, Sung Jung;Hong, Ki Chang;Jeon, Gwang Joo;Kong, Hong Sik;Lee, Jun Heon
    • Asian-Australasian Journal of Animal Sciences
    • /
    • v.18 no.10
    • /
    • pp.1368-1374
    • /
    • 2005
  • To investigate the genetic relationships among various cattle breeds, bovine mtDNA D-loop region was used in 411 animals of 18 cattle breeds, including 8 Asian Bos taurus, 7 European Bos taurus, 1 Asian Bos indicus, and 2 African Bos indicus. The size of amplified PCR products from mtDNA D-loop region was 964 bp and the products were digested by 15 different restriction enzymes. Two different band patterns were identified in eight restriction enzymes (BstXI, Hae III, Msp I, Apa I, Taq I, Alu I, BamH I, EcoN I) and the rest of restriction enzymes showed more than 3 different band patterns among which Apo I and MspR9 resulted in 7 different restriction patterns. The genotypes, number of haplotype, effective number of haplotype, and degree of heterozygosity were analyzed. Based on all the PCR-RFLP data, different haplotypes were constructed and analyzed for calculating genetic distances between these breeds using Nei's unbiased method and constructing a phylogenetic tree.

Analysis and Design of a Forming Porcess for Combined Extrusion with Aluminum AIIoy 7075 (알루미늄 7075 복합압출재에 대한 공정해석 및 설계)

  • 김진복;변상규
    • Transactions of Materials Processing
    • /
    • v.6 no.5
    • /
    • pp.446-455
    • /
    • 1997
  • A Combined extrusion operation consists of forward and backward extrusion forming and it is possible to make the process be simple by employing it. But the metal flow pattern induced by the operation is hard to analyze accurately because the flows are non-steady, which have at least two directions dependent upon each other. So engineers in the industrial factories had conducted the two extrusion operations separately. A new process was designed by the industrial expert for forming of an alu-minum preform using the combined extrusion operation. In this study, experiments and finite element analysis was carried out to determine the process parameters. Through the preliminary experiment, it was shown that warm forming condition was more desirable than cold or hot ones. And optimal shape of initial billet could be also determined. From the compatibility test, bonde-lube was chosen as the optimal lubricant and 20$0^{\circ}C$ as the material temperature by the inspection of micro-structure. The operation was simulated by the rigid-plastic finite element method to examine the metal flow. Disap-pearing of dead metal zone was observed as the punch fell down and desirable shape was obtained from the one operation. As a result of this study, 7 operations could be reduced and 225% of material saved.

  • PDF

Bit Error Rate measurement of an RSFQ switch by using an automatic error counter (자동 Error counter를 이용한 RSFQ switch 소자의 Bit Error Rate 측정)

  • Kim Se Hoon;Kim Jin Young;Baek Seung Hun;Jung Ku Rak;Hahn Taek Sang;Kang Joon Hee
    • Progress in Superconductivity and Cryogenics
    • /
    • v.7 no.1
    • /
    • pp.21-24
    • /
    • 2005
  • The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been very important issue. So in this experiment, we calculated error rate of RSFQ switch in superconductiyity ALU, The RSFQ switch should have a very low error rate in the optimal bias. We prepared two circuits Placed in parallel. One was a 10 Josephson transmission lines (JTLs) connected in series, and the other was the same circuit but with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to the both circuits. The outputs of the two circuits were compared with an RSFQ XOR to measure the error rate of the RSFQ switch. By using a computerized bit error rate test setup, we measured the bit error rate of 2.18$\times$$10^{12}$ when the bias to the RSFQ switch was 0.398mh that was quite off from the optimum bias of 0.6mA.

Functional-Level Design and Simulation of a Graphics Processor (그래픽스 프로세서의 기능적 설계 및 시뮬레이션)

  • Bae, Seong-Ok;Lee, Hee-Choul;Kyung, Chong-Min
    • Journal of the Korean Institute of Telematics and Electronics
    • /
    • v.25 no.10
    • /
    • pp.1252-1262
    • /
    • 1988
  • This paper describes a functional-level design and simulation of Graphics Processor(GP) which can be used in various graphics systems. GP is divided into two parts: One is CPU, and the other is the interface to I/O peripherals. In order to achieve fast execution of graphics instructions, the CPU has special ALU, barrel shifter and window comparator and a FIFO for instruction prefetch. I/O part controls the DRAM and VRAM which constitute the GP's local memory, generates the signals to drive monitor, and communicates with the host processor. The functional simulation of CPU was done on Daisy workstation while the I/O part was designed using GENESIL, a silicon compiler.

  • PDF